Laterally unconfined structure
View Patent ↗Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.
1. A method, comprising:
forming a cavity in a first surface of a first substrate, wherein the first substrate comprises a second surface opposite the first surface;
forming a conductive seed layer within the cavity, the conductive seed layer lining at least a portion of sidewalls of the cavity;
masking the first surface and the cavity with a patterned mask, the patterned mask lining at least a portion of the conductive seed layer at the sidewalls of the cavity;
forming one or more first embedded conductive interconnect structures within the cavity;
planarizing the first surface of the first substrate to form a first planarized bonding surface opposite the second surface and comprising an exposed surface of the one or more first embedded conductive interconnect structures; and
removing the patterned mask to reveal a vertical isolation gap disposed between the conductive seed layer and the one or more first embedded conductive interconnect structures.
2. The method of claim 1 , further comprising forming the one or more first embedded conductive interconnect structures by filling the cavity using a damascene process.
3. The method of claim 2 , further comprising filling the cavity with a conductive material, through the patterned mask.
4. The method of claim 2 , further comprising filling the cavity with multiple layers of different conductive materials, through the patterned mask.
5. The method of claim 4 , further comprising separating one or more of the multiple layers with a diffusion barrier layer.
6. The method of claim 1 , further comprising:
forming one or more second embedded conductive interconnect structures in a second substrate having opposing first and second surfaces;
planarizing the first surface of the second substrate to form a second planarized bonding surface opposite the second surface of the second substrate and comprising an exposed surface of the one or more second embedded conductive interconnect structures;
bonding the second planarized bonding surface of the second substrate to the first planarized bonding surface of the first substrate via direct bonding without adhesive, at a first temperature; and
directly bonding the one or more second embedded conductive interconnect structures to the one or more first embedded conductive interconnect structures at a second temperature, less than or equal to the first temperature.
7. The method of claim 1 , further comprising lining one or more sides of the vertical isolation gap with a diffusion barrier layer.
8. The method of claim 1 , further comprising filling the vertical isolation gap and/or surrounding the one or more first embedded conductive interconnect structures with a predetermined adhesive barrier layer having anisotropic lateral adhesive properties, the predetermined adhesive barrier layer being strongly bonded to the one or more first embedded conductive interconnect structures and weakly bonded to material of the first substrate.
9. A method, comprising:
forming one or more first embedded conductive interconnect structures within a cavity in a first surface of a first substrate, wherein the first substrate comprises a second surface opposite the first surface;
planarizing the first surface of the first substrate to form a first planarized bonding surface opposite the second surface and comprising an exposed surface of the one or more first embedded conductive interconnect structures;
masking the first planarized bonding surface with a patterned mask, the patterned mask including one or more openings over the first surface at a perimeter of the cavity;
selectively removing portions of the first substrate corresponding to the openings in the patterned mask; and
removing the patterned mask to reveal one or more vertical isolation gaps disposed between the one or more first embedded conductive interconnect structures and the material of the first substrate.
10. The method of claim 9 , further comprising lining one or more sides of the one or more vertical isolation gaps with a diffusion barrier layer.
11. The method of claim 9 , further comprising filling the one or more vertical isolation gaps with a compressible material, and wherein the compressible material is disposed between the one or more first embedded conductive interconnect structures and the material of the first substrate.
12. The method of claim 9 , further comprising filling the one or more vertical isolation gaps and/or surrounding the one or more first embedded conductive interconnect structures with a predetermined adhesive barrier layer having anisotropic lateral adhesive properties, the predetermined adhesive barrier layer being strongly bonded to the one or more first embedded conductive interconnect structures and weakly bonded to material of the first substrate.
13. The method of claim 9 , further comprising forming the one or more first embedded conductive interconnect structures to have a predetermined grain texture orientation.
14. A method, comprising:
forming a cavity in a first surface of a first substrate, wherein the cavity comprises at least one sidewall and wherein the first substrate comprises a second surface opposite the first surface;
forming a patterned mask over the substrate, wherein the patterned mask covers at least a portion of the at least one sidewall;
forming a conductive interconnect structure within the cavity;
planarizing the first substrate to form a planarized bonding surface opposite the second surface, wherein the planarized bonding surface comprises an exposed surface of the conductive interconnect structure; and
removing the patterned mask to reveal a vertical isolation gap between the at least one sidewall and the conductive interconnect structure.
15. The method of claim 14 , further comprising:
before forming the patterned mask over the substrate, forming a conductive seed layer within the cavity, wherein a portion of the conductive seed layer covers the portion of the at least one sidewall and wherein forming the patterned mask over the substrate comprises forming the patterned mask such that it lines the portion of the conductive seed layer.
16. The method of claim 15 , wherein portion of the conductive seed layer comprises a first portion of the conductive seed layer, wherein forming the conductive seed layer within the cavity comprises forming the conductive seed layer within the cavity such that a second portion of the conductive seed layer at least partially covers a bottom surface of the cavity, and wherein forming the conductive interconnect structure within the cavity comprises forming the conductive interconnect structure within the cavity such that it at least partially covers the second portion of the conductive seed layer.
17. The method of claim 15 , wherein the vertical isolation gap is between the conductive seed layer and the conductive interconnect structure.
18. The method of claim 15 , wherein the conductive seed layer comprises copper.
19. The method of claim 14 , further comprising:
after removing the patterned mask, forming a barrier layer within the vertical isolation gap.
20. The method of claim 14 , further comprising:
before forming the patterned mask over the substrate, forming a barrier layer within the cavity.