High performance trace offload circuit architecture
An integrated circuit includes a compute circuit and a trace data mover circuit coupled to the compute circuit. The trace data mover circuit is configured to convey trace data generated by the compute circuit to a destination circuit. The trace data mover circuit includes a controller circuit configured to receive a stream of trace data from the compute circuit and generate instructions for writing the trace data. The trace data mover circuit includes a writer circuit configured to write the trace data to the destination circuit responsive to the instructions generated by the controller circuit.
1 . An integrated circuit, comprising:
a compute circuit; and
a trace data mover circuit coupled to the compute circuit and configured to convey trace data generated by the compute circuit to a destination circuit;
wherein the trace data mover circuit includes:
a controller circuit configured to receive a stream of trace data from the compute circuit and generate instructions for writing the trace data; and
a writer circuit configured to write the trace data to the destination circuit using burst data transfers responsive to the instructions generated by the controller circuit;
wherein the controller circuit is coupled to the writer circuit through a data queue configured to store the trace data and an instruction queue configured to store the instructions generated by the controller circuit; and
wherein the controller circuit is configured to enqueue a flush instruction to the instruction queue in response to receiving a flush request from a host processor, the flush instruction instructing the writer circuit to flush data from the data queue.
2 . The integrated circuit of claim 1 , wherein an amount of data flushed in response to the flush request is less than an amount of data for a burst data transfer.
3 . The integrated circuit of claim 1 , wherein the writer circuit obtains the instructions from the instruction queue and, in response to execution of the instructions as obtained, writes the trace data to the destination circuit.
4 . The integrated circuit of claim 1 , wherein the compute circuit is implemented as a Coarse Grain Reconfigurable Architecture compute circuit.
5 . The integrated circuit of claim 1 , wherein the compute circuit is implemented as a data processing array.
6 . The integrated circuit of claim 1 , further comprising:
programmable logic coupled to the compute circuit, wherein the trace data mover circuit is implemented in the programmable logic.
7 . The integrated circuit of claim 1 , wherein the destination circuit is a memory.
8 . The integrated circuit of claim 1 , further comprising:
a network-on-chip coupling the trace data mover circuit to the destination circuit.
9 . The integrated circuit of claim 1 , wherein the trace data mover circuit is runtime configurable.
10 . The integrated circuit of claim 1 , wherein the burst data transfers have a configurable size.
11 . The integrated circuit of claim 1 , wherein the trace data mover circuit is configurable to write data to the destination circuit using a linear mode or a circular mode.
12 . A method, comprising:
in response to receiving, by a controller circuit of a trace data mover circuit, a data stream of trace data from a compute circuit, storing the trace data within a data queue of the trace data mover circuit;
generating, by the controller circuit, a plurality of instructions for writing the trace data to a destination circuit and storing the plurality of instructions in an instruction queue of the trace data mover circuit; and
writing, by a writer circuit, the trace data obtained from the data queue to the destination circuit using burst data transfers in response to executing the plurality of instructions obtained from the instruction queue;
wherein the controller circuit is coupled to the writer circuit through the data queue and the instruction queue; and
enqueuing, by the controller circuit, a flush instruction to the instruction queue in response to receiving a flush request from a host processor, wherein the flush instruction instructs the writer circuit to flush data from the data queue.
13 . The method of claim 12 , wherein a size of the burst data transfers is configurable.
14 . The method of claim 12 , wherein the writer circuit is configurable to write the trace data to the destination circuit using a linear mode or a circular mode.
15 . The method of claim 12 , wherein an amount of data flushed in response to the flush request is less than an amount of data for a burst data transfer.