System-on-chip with master/slave debug interface
A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave debug interface, wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data.
1. A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave debug interface, wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data.
2. The SOC debugging system of claim 1 , wherein the master SOC comprises a user interface.
3. The SOC debugging system of claim 2 , wherein the user interface is a USB interface.
4. The SOC debugging system of claim 2 , wherein the user interface is a network interface.
5. The SOC debugging system of claim 2 , wherein the user interface is a wireless interface.
6. The SOC debugging system of claim 1 , wherein the transactions include instructions to store data in memories of the SOCs, and to read data from the memories of the SOCs.
7. The SOC debugging system of claim 6 , wherein the master SOC comprises a user interface, and the transactions further include instructions to transfer data to and from a host system via the user interface.
8. The SOC debugging system of claim 1 , wherein the master/slave debug interface is a two pin debug interface including one pin for a clock signal and another pin for bidirectional data.
9. The SOC debugging system of claim 1 , wherein the at least one master SOC can be configured to function as a tool hardware front-end for the shared debug bus.
10. The SOC debugging system of claim 1 , wherein the at least one master SOC functions as a bus bridge between a host system and the shared debug bus.
11. The SOC debugging system of claim 1 , wherein the at least one master SOC is connected to a host system through the user interface and accesses the non-master SOCs indirectly through the at least one master SOC.
12. The SOC debugging system of claim 1 , wherein the at least one master SOC includes software acting as a debug monitor.
13. The SOC debugging system of claim 1 , wherein the at least one master SOC includes a trace buffer for capturing traces from the other SOCs.