Marchand baluns in coreless package substrates
In examples, a semiconductor package comprises a conductive terminal; a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and a substrate coupled to the conductive terminal and to the device side of the semiconductor die. The substrate includes a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal. The substrate includes a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die. The first and second metal layers form a Marchand balun.
1 . A semiconductor package, comprising:
a conductive terminal;
a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and
a substrate coupled to the conductive terminal and to the device side of the semiconductor die, the substrate including:
a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal; and
a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die,
wherein the first and second metal layers form a Marchand balun.
2 . The semiconductor package of claim 1 , wherein the first metal layer includes a first portion including multiple segments in parallel with each other, and wherein the first metal layer includes a second portion including multiple segments in parallel with each other.
3 . The semiconductor package of claim 2 , wherein the first portion includes a first segment in parallel with a second segment of the second portion.
4 . The semiconductor package of claim 2 , wherein a segment in the first portion has a width that is less than a width of a segment in the second portion.
5 . The semiconductor package of claim 1 , wherein the second metal layer includes a first portion including multiple segments in parallel with each other, and wherein the second metal layer includes a second portion including multiple segments in parallel with each other.
6 . The semiconductor package of claim 5 , wherein a first end of the first portion and a second end of the second portion are coupled to each other.
7 . The semiconductor package of claim 1 , wherein the substrate is a coreless substrate.
8 . A semiconductor package, comprising:
a conductive terminal;
a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and
a substrate coupled to the conductive terminal and to the device side of the semiconductor die, the substrate including:
a first metal layer having a differential input extending toward and coupled to either the conductive terminal or the semiconductor die, the first metal layer having a first serpentine portion including multiple segments in parallel with each other and a second serpentine portion including multiple segments in parallel with each other, the first serpentine portion including multiple segments in parallel with multiple segments in the second serpentine portion, the first and second serpentine portions having ends coupled to each other; and
a second metal layer having a single input extending toward and coupled to either the semiconductor die or the conductive terminal, the second metal layer having a third serpentine portion including multiple segments in parallel with each other and a fourth serpentine portion including multiple segments in parallel with each other, the third serpentine portion including multiple segments in parallel with multiple segments in the fourth serpentine portion, the third and fourth serpentine portions having ends coupled to each other, the first serpentine portion vertically aligned with the third serpentine portion and the second serpentine portion vertically aligned with the fourth serpentine portion.
9 . The semiconductor package of claim 8 , wherein the first and second metal layers form a Marchand balun.
10 . The semiconductor package of claim 8 , wherein a width of a segment in the first serpentine portion is less than a width of a segment in the second serpentine portion.
11 . The semiconductor package of claim 10 , wherein a width of a segment in the third serpentine portion is less than a width of a segment in the fourth serpentine portion.
12 . The semiconductor package of claim 11 , wherein a ratio of the width of the first serpentine portion to the width of the second serpentine portion is greater than a ratio of the width of the third serpentine portion to the width of the fourth serpentine portion.
13 . The semiconductor package of claim 8 , wherein the substrate is a coreless substrate.