Method and system for performing read and write operations in cells of a NAND memory
Example embodiments of the present disclosure disclose method and system for performing read/write operations in NAND memory. A memory controller of the NAND memory receives write request from host controller to write data present in set of support cell blocks of NAND memory into a ‘n’-level cell block of NAND memory. The write request includes information about mapping between set of support cell blocks and ‘n’-level cell block. The mapping between set of support cell blocks and ‘n’-level cell block is used to update L2P table ( 206 ). Further, memory controller performs copyback operation on set of support cell blocks for writing data to ‘n’-level cell block based on L2P table using NAND latches. On receiving read request, host controller retrieves data from at least one support cell block associated with ‘n’-level cell block based on mapping on determining ‘n’-level cell block is listed in active block list.
1. A method for writing data into cells of a NOT-AND (NAND) memory, the NAND memory including a plurality of non-volatile memory cells and one or more volatile NAND latches configured to temporarily store data before writing the data to the plurality of non-volatile memory cells, the method comprising:
receiving, by a memory controller of the NAND memory, a write request from a host controller to write data present in a set of support cell blocks of the NAND memory into a ‘n’-level cell block of the NAND memory, wherein the write request comprises information on mapping from each page of the set of support cell blocks to a corresponding page in the ‘n’-level cell block;
updating, by the memory controller, a Logical to Physical (L2P) table based on the mapping between the set of support cell blocks and the ‘n’-level cell block; and
performing, by the memory controller, a copyback operation on the set of support cell blocks for writing the data to the ‘n’-level cell block based on the L2P table using the one or more volatile NAND latches as hardware accelerators configured to perform the copyback operation as an internal copyback operation without the host controller tracking intermediate single-level cell (SLC) locations in the L2P table.
2. The method as claimed in claim 1 , wherein the ‘n’-level cell block is one of: a Multi-Level Cell (MLC) block, a Triple Level Cell (TLC) block, a Quad Level Cell (QLC) block and a Penta Level Cell (PLC) block.
3. The method as claimed in claim 1 , wherein the set of support cell blocks are among a plurality of support cell blocks which are idle.
4. The method as claimed in claim 3 , wherein the plurality of support cell blocks comprise one or more of: a Single Level Cell (SLC) block, a Multi-Level Cell (MLC) block, a Triple Level Cell (TLC) block, a Quad Level Cell (QLC) block and a Penta Level Cell (PLC) block.
5. The method as claimed in claim 1 , wherein the set of support cell blocks and the ‘n’-level cell block are listed in an active block list based on the mapping, and wherein the active block list provides information on non-idle ‘n’-level cell blocks and non-idle support cell blocks.
6. The method as claimed in claim 1 , wherein the set of support cell blocks are in an idle support cell block pool after the copyback operation.
7. A method for reading data from cells in a NOT-AND (NAND) memory, the method comprising:
receiving, by a memory controller of a NAND memory, a read request from a host controller to read data from an ‘n’-level cell block of the NAND memory;
checking, by the memory controller, if the ‘n’-level cell block of the NAND memory is listed in an active block list, wherein the active block list comprises information on non-idle ‘n’-level cell blocks and non-idle support cell blocks;
obtaining, by the memory controller, a mapping from each page of a set of support cell blocks to a corresponding page in the ‘n’-level cell block based on determining the ‘n’-level cell block of the NAND memory is listed in the active block list; and
retrieving, by the memory controller, the data by,
retrieving the data from at least one support cell block of the set of support cell blocks associated with the ‘n’-level cell block based on the mapping, in response to the ‘n’-level cell block being in the active block list, and
retrieving the data from the ‘n’-level cell block based on a Logical to Physical (L2P) table, in response to the ‘n’-level cell block not being in the active block list,
wherein the data from the at least one support cell block is provided to the host controller.
8. The method as claimed in claim 7 , wherein the data is retrieved from the ‘n’-level cell block based on determining the ‘n’-level cell block is not in the active block list based on a Logical to Physical (L2P) table.
9. The method as claimed in claim 7 , wherein the at least one support cell block is identified from the set of support cell blocks based on the mapping and the read request.
10. A memory controller for writing data into cells of a NOT-AND (NAND) memory, the NAND memory including a plurality of non-volatile memory cells and one or more volatile NAND latches configured to temporarily store data before writing the data to the plurality of non-volatile memory cells, the memory controller comprising:
a memory configured to store instructions; and
a processor configured to execute the instructions stored in the memory and cause the memory controller to
receive a write request from a host controller to write data present in a set of support cell blocks of the NAND memory into a ‘n’-level cell block of the NAND memory, wherein the write request comprises information on mapping from each page of the set of support cell blocks to a corresponding page in the ‘n’-level cell block,
update a Logical to Physical (L2P) table based on the mapping between the set of support cell blocks and the ‘n’-level cell block, and
perform a copyback operation on the set of support cell blocks for writing the data to the ‘n’-level cell block based on the L2P table using the one or more volatile NAND latches as hardware accelerators that perform the copyback operation as an internal copyback operation without the host controller tracking intermediate single-level cell (SLC) locations in the L2P table.
11. The memory controller as claimed in claim 10 , wherein the ‘n’-level cell block is one of: a Multi-Level Cell (MLC) block, a Triple Level Cell (TLC) block, a Quad Level Cell (QLC) block and a Penta Level Cell (PLC) block.
12. The memory controller as claimed in claim 10 , wherein the processor is configured to execute the instructions stored in the memory such that the set of support cell blocks are among a plurality of support cell blocks which are idle.
13. The memory controller as claimed in claim 12 , wherein the plurality of support cell blocks comprise one or more of: a Single Level Cell (SLC) block, a Multi-Level Cell (MLC) block, a Triple Level Cell (TLC) block, a Quad Level Cell (QLC) block and a Penta Level Cell (PLC) block.
14. The memory controller as claimed in claim 10 , wherein the processor is configured to execute the instructions stored in the memory such that the set of support cell blocks and the ‘n’-level cell block are listed in an active block list based on the mapping, and wherein the active block list provides information on non-idle ‘n’-level cell blocks and non-idle support cell blocks.
15. The memory controller as claimed in claim 10 , wherein the processor is configured to execute the instructions stored in the memory such that the set of support cell blocks are in an idle support cell block pool after the copyback operation.