Handling defective memory blocks of NAND memory devices
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.
1. A NAND memory device comprising:
a memory array comprising a plurality of memory blocks;
a plurality of block select circuits, the block select circuits respectively coupled to the memory blocks; and
a plurality of volatile latches, the volatile latches respectively coupled to the block select circuits;
wherein each volatile latch is adapted to selectively prevent activation of the respective block select circuit coupled thereto so as to prevent testing of the memory block coupled to that block select circuit when that memory block is a known defective block; and
wherein each volatile latch is further adapted to indicate a pass status for its respective block when that block is known to be defective and when the memory device is operating in a test mode.
2. The NAND memory device of claim 1 , wherein each volatile latch is further adapted to provide an indication of its state.
3. The NAND memory device of claim 1 , wherein each volatile latch is further adapted to selectively allow testing of the respective memory block coupled thereto when the memory block is not indicated to be defective.
4. The NAND memory device of claim 1 further comprises a plurality of non-volatile latches, the non-volatile latches respectively coupled to the block select circuits.
5. The NAND memory device of claim 1 further comprises a plurality of fusible elements, the fusible elements respectively coupled to the block select circuits.
6. A NAND memory device comprising:
a memory array comprising a plurality of memory blocks;
a plurality of block select circuits, the block select circuits respectively coupled to the memory blocks;
a plurality of volatile latches, the volatile latches respectively coupled to the block select circuits; and
a plurality of non-volatile latches, the non-volatile latches respectively coupled to the block select circuits;
wherein each volatile latch is adapted to selectively prevent activation of the respective block select circuit coupled thereto so as to prevent testing of the memory block coupled to that block select circuit when that memory block is a known defective memory block; and
wherein each non-volatile latch is adapted to permanently prevent activation, during normal operation of the memory device, of the respective block select circuit coupled thereto so as to permanently prevent access to the memory block coupled to that block select circuit when that memory block is a known defective memory block.
7. The NAND memory device of claim 6 , wherein each volatile latch is further adapted to provide an indication of its state.
8. The NAND memory device of claim 6 , wherein each volatile latch is further adapted to selectively allow testing of the respective memory block coupled thereto when the memory block is not indicated to be defective.
9. The memory NAND device of claim 6 , wherein each non-volatile latch is further adapted to provide a control signal, during normal operation of the memory device, to modify voltage pump trims of the memory device when that block select circuit is coupled to a known defective memory block.
10. The memory NAND device of claim 6 , wherein each non-volatile latch comprises fuses and/or anti-fuses.
11. A NAND memory device comprising:
a memory array comprising a plurality of memory blocks;
a block select circuit coupled to each of the memory blocks;
a decoder coupled to each of the block select circuits;
a volatile latch coupled to each of the decoders and each of the block select circuits; and
a non-volatile latch coupled to each of the decoders and each of the block select circuits;
wherein each volatile latch is adapted to selectively prevent activation of the respective block select circuit coupled thereto so as to prevent testing of the memory block coupled to that block select circuit when that memory block is a known defective memory block;
wherein each non-volatile latch is adapted to permanently prevent activation, during normal operation of the memory device, of the respective block select circuit coupled thereto so as to permanently prevent access to the memory block coupled to that block select circuit when that memory block is a known defective memory block;
wherein each volatile latch is further adapted to selectively allow testing of the respective memory block coupled thereto when the memory block is not indicated to be defective; and
wherein each volatile latch is further adapted to provide an indication of its state.
12. The memory NAND device of claim 11 , wherein each non-volatile latch is further adapted to provide a control signal, during normal operation of the memory device, to modify voltage pump trims of the memory device when that block select circuit is coupled to a known defective memory block.
13. A method of operating a NAND memory device, comprising:
during a test mode of operation:
when a memory block of a memory array of the memory device is determined to be defective, setting a volatile latch of the memory array corresponding to the memory block to a first state so as to prevent testing of the memory block;
indicating a pass condition for the memory block while the volatile latch is at the first state; and
when the memory block is indicated as being non-defective, setting the volatile latch of the memory array to a second state so as to allow testing of the memory block; and
during a normal mode of operation:
permanently preventing the known defective block of a memory array from being accessed by using a fusible element to permanently prevent activation of a block select circuit that is coupled to the fusible element and the defective memory block.
14. The method of claim 13 , wherein, during the normal mode of operation, when an attempt is made to access the defective block, modifying voltage trims if the fusible element indicates a known defect.
15. The method of claim 14 , wherein, during the normal mode of operation, modifying the voltage trims is in response to receiving a command signal from control circuitry of the memory device at the fusible element when the attempt is made to access the defective block.
16. The method of claim 13 , wherein, during the test mode of operation, indicating a pass condition comprises the volatile latch providing a control signal to a tester connected to the memory device.
17. The method of claim 13 , wherein, during the test mode of operation, setting the volatile latch to the first state prevents activation of a block select circuit coupled to the memory block and the volatile latch to prevent access to the memory block.
18. The method of claim 13 , wherein, during the normal mode of operation, indicating an error when an attempt is made to access the defective block.