Enhanced microstrip trace
A printed circuit board comprising a primary dielectric layer disposed underneath a microstrip trace and a secondary dielectric layer disposed above portions of the primary dielectric layer and the microstrip trace. The printed circuit board also includes a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded.
1 . A printed circuit board comprising:
a primary dielectric layer disposed underneath a microstrip trace;
a secondary dielectric layer disposed above portions of the primary dielectric layer and the microstrip trace; and
a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded, wherein the conductive plane is comprised of a conductive silk screen.
2 . The printed circuit board of claim 1 , wherein the secondary dielectric layer has a dielectric constant that is similar to a pre-impregnated material of the primary dielectric layer.
3 . The printed circuit board of claim 1 , wherein the secondary dielectric layer has a dielectric constant that is lower to a pre-impregnated material of the primary dielectric layer.
4 . The printed circuit board of claim 1 , wherein the secondary dielectric layer is disposed between the primary dielectric layer and the conductive plane.
5 . The printed circuit board of claim 1 , wherein the conductive plane is grounded through an exposed copper.
6 . The printed circuit board of claim 1 , wherein the secondary dielectric layer is comprised of a solder mask.
7 . The printed circuit board of claim 6 , wherein the solder mask is applied using multiple coats.
8 . The printed circuit board of claim 1 , wherein the conductive plane is mixed on epoxy paint.
9 . The printed circuit board of claim 1 , wherein signal integrity performance of the microstrip trace is similar to a stripline trace.
10 . An information handling system, comprising:
a processor; and
a printed circuit board further comprising:
a primary dielectric layer disposed underneath a microstrip trace;
a secondary dielectric layer disposed above the primary dielectric layer and the microstrip trace; and
a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded, wherein the conductive plane is comprised of a conductive silk screen.
11 . The information handling system of claim 10 , wherein the secondary dielectric layer has a dielectric constant that is similar to a pre-impregnated material of the primary dielectric layer.
12 . The information handling system of claim 10 , wherein the secondary dielectric layer has a dielectric constant that is lower to a pre-impregnated material of the primary dielectric layer.
13 . The information handling system of claim 10 , wherein the secondary dielectric layer is disposed between the primary dielectric layer and the conductive plane.
14 . The information handling system of claim 10 , wherein the conductive plane is grounded through an exposed copper.
15 . The information handling system of claim 10 , wherein the secondary dielectric layer is comprised of a solder mask.
16 . A method comprising:
providing a primary dielectric layer disposed underneath a microstrip trace;
providing a secondary dielectric layer disposed above portions of the primary dielectric layer and the microstrip trace; and
providing a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded, wherein the conductive plane is comprised of a conductive silk screen.
17 . The method of claim 16 , wherein the secondary dielectric layer has a dielectric constant that is similar to a pre-impregnated material of the primary dielectric layer.
18 . The method of claim 16 , wherein the secondary dielectric layer has a dielectric constant that is lower to a pre-impregnated material of the primary dielectric layer.
19 . The method of claim 16 , wherein the secondary dielectric layer is disposed between the primary dielectric layer and the conductive plane.
20 . The method of claim 16 , wherein a solder mask is applied using multiple coats.