Three-dimensional nor array and method of making the same
A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.
1. A three-dimensional memory device, comprising:
first vertical stacks of first field effect transistor strings; and
second vertical stacks of second field effect transistor strings,
wherein:
the first vertical stacks alternate with the second vertical stacks along a first horizontal direction;
each of the first field effect transistor strings comprises a series connection of a respective set of first field effect transistors that are electrically connected to each other such that each neighboring pair of first field effect transistors share a respective one of a plurality of first source/drain regions;
each of the second field effect transistor strings comprises a series connection of a respective set of second field effect transistors that are electrically connected to each other such that each neighboring pair of second field effect transistors share a respective one of the second source/drain region;
the series connection of the respective set of first field effect transistors shares a respective one of a plurality of word lines;
the first source/drain regions are located in different vertical levels in respective first source/drain pillar structures; and
the second source/drain regions are located in different vertical levels in respective second source/drain pillar structures.
2. The three-dimensional memory device of claim 1 , further comprising:
first bit lines electrically connected to a respective subset of the first source/drain pillar structures; and
second bit lines electrically connected to a respective subset of the second source/drain pillar structures.
3. The three-dimensional memory device of claim 2 , wherein:
each neighboring pair of one of the first field effect transistor strings and one of the second field effect transistor strings shares the respective one of the plurality of word lines;
the plurality of word lines are laterally spaced apart along the first horizontal direction;
the first bit lines are located below the first source/drain pillar structures; and
the second bit lines are located above the second source/drain pillar structures.
4. The three-dimensional memory device of claim 1 , wherein:
each of the first field effect transistor strings comprises a respective first memory film that continuously extends through and is shared by the respective series connection of first field effect transistors; and
each of the second field effect transistor strings comprises a respective second memory film that continuously extends through and is shared by the respective series connection of second field effect transistors.
5. The three-dimensional memory device of claim 1 , wherein each of the first field effect transistors comprise a respective pair of charge storage material portions.
6. A method of operating a three-dimensional memory device comprising first vertical stacks of first field effect transistor strings; and second vertical stacks of second field effect transistor strings, wherein: the first vertical stacks alternate with the second vertical stacks along a first horizontal direction; each of the first field effect transistor strings comprises a series connection of a respective set of first field effect transistors that are electrically connected to each other such that each neighboring pair of first field effect transistors share a respective one of a plurality of first source/drain regions; each of the second field effect transistor strings comprises a series connection of a respective set of second field effect transistors that are electrically connected to each other such that each neighboring pair of second field effect transistors share a respective one of the second source/drain region; the series connection of the respective set of first field effect transistors shares a respective one of a plurality of word lines; the first source/drain regions are located in different vertical levels in respective first source/drain pillar structures; and the second source/drain regions are located in different vertical levels in respective second source/drain pillar structures, the method comprising:
applying 0V to a first source/drain region located on a first side of a semiconductor channel of a selected first field effect transistor;
applying a drain-side programming bias voltage to another first source/drain region located on a second side of the semiconductor channel of the selected first field effect transistor; and
applying a gate programming bias voltage to a first word line of the selected first field effect transistor to program the selected first field effect transistor.
7. The method of claim 6 , further comprising:
allowing the first and the second source/drain regions of respective unselected ones of the first and second field effect transistors to float during the programming of the selected first field effect transistor; and
allowing to float all of the plurality of word lines other than the first word line during the programming of the selected first field effect transistor.
8. The method of claim 7 , wherein:
the selected first field effect transistor comprises a first charge storage material portion located adjacent to the first side of the semiconductor channel, and a second charge storage material portion located adjacent to the second side of the semiconductor channel; and
the second charge storage material portion corresponding to a second data bit is programmed by channel hot electron injection during the programming of the selected first field effect transistor without programming the first charge storage material portion corresponding to a first data bit.
9. The method of claim 8 , further comprising:
applying 0V to the first source/drain region located on the second side of the semiconductor channel of the selected first field effect transistor;
applying the drain-side programming bias voltage to the first source/drain region located on the first side of the semiconductor channel of the selected first field effect transistor; and
applying the gate programming bias voltage to the first word line of the selected first field effect transistor to program the first charge storage material portion corresponding to the first data bit by channel hot electron injection without programming the second charge storage material portion corresponding to the second data bit.
10. The method of claim 9 , further comprising:
allowing the first and the second source/drain regions of respective unselected ones of the first and second field effect transistors to float during the programming of the first data bit of the selected first field effect transistor; and
allowing to float all of the plurality of word lines other than the first word line during the programming of the first data bit of the selected first field effect transistor.
11. The method claim 8 , further comprising:
applying a positive erase bias voltage to the first source/drain region located on the first side of the semiconductor channel of the selected first field effect transistor;
allowing to float the first source/drain region located on the second side of the semiconductor channel of the selected first field effect transistor; and
applying the negative erase bias voltage to the first word line of the selected first field effect transistor to erase the second data bit by hot hole injection without erasing the second data bit of the selected first field effect transistor.
12. The method of claim 11 , further comprising:
allowing the first and the second source/drain regions of respective unselected ones of the first and second field effect transistors to float during the erasing of the second data bit of the selected first field effect transistor; and
allowing to float all of the plurality of word lines other than the first word line during the erasing of the second data bit of the selected first field effect transistor.
13. The method of claim 8 , further comprising:
applying 0V to the first source/drain region located on the first side of the semiconductor channel of the selected first field effect transistor;
applying a bit line read bias voltage to the first source/drain region located on the second side of the semiconductor channel of the selected first field effect transistor; and
applying a gate read bias voltage to the first word line of the selected first field effect transistor to read the second data bit of the selected first field effect transistor.
14. The method of claim 13 , further comprising:
allowing the first and the second source/drain regions of respective unselected ones of the first and second field effect transistors to float during the reading of the second data bit of the selected first field effect transistor; and
allowing to float all of the plurality of word lines other than the first word line during the reading of the second data bit of the selected first field effect transistor.
15. The method of claim 6 , further comprising:
applying 0V to each first source/drain region within the first field effect transistor string that is located on the first side of the semiconductor channel of the selected first field effect transistor; and
applying the drain-side programming bias voltage to each first source/drain region within the first field effect transistor string that is located on the second side of the semiconductor channel of the selected first field effect transistor.
16. The method of claim 15 , further comprising:
applying the drain-side programming bias voltage to each of the second source/drain regions during programming of the selected first field effect transistor; and
applying 0V to all of the plurality of word lines other than the first word line during the programming of the selected first field effect transistor.
17. The method of claim 16 , wherein:
the selected first field effect transistor comprises a first charge storage material portion located adjacent to the first side of the semiconductor channel, and a second charge storage material portion located adjacent to the second side of the semiconductor channel; and
the second charge storage material portion corresponding to a second data bit is programmed during the programming of the selected first field effect transistor without programming the first charge storage material portion corresponding to a first data bit.
18. The method of claim 17 , further comprising:
applying 0V to each first source/drain region within the first field effect transistor string that is located on the first side of the semiconductor channel of the selected first field effect transistor;
applying a bit line read bias voltage to each first source/drain region within the first field effect transistor string that is located on the second side of the semiconductor channel of the selected first field effect transistor; and
applying a gate read bias voltage to the first word line of the selected first field effect transistor to read the second data bit of the selected first field effect transistor.
19. The method of claim 16 , wherein the second data bit of the selected first field effect transistor is read without reading the first data bit of the selected first field effect transistor.
20. The method of claim 15 , further comprising erasing the three-dimensional memory device by:
applying an erase bias voltage to the first and the second source/drain regions; and
applying 0V each of the plurality of word lines.