Sub-sampling phase locked loop (SSPLL) with saturated reference feedback
A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.
1. A phase locked loop (PLL), comprising:
a phase detector configured to
receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency,
sample the feedback signal, and
output a phase detection signal indicative of a phase of the feedback signal;
a voltage controlled oscillator configured to generate an output signal based on the phase detection signal, wherein the output signal has an output frequency greater than the reference frequency; and
feedback circuitry configured to
detect a signal edge of the output signal, and
selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.
2. The PLL of claim 1 , wherein the PLL is a sub-sampling PLL (SSPLL).
3. The PLL of claim 1 , wherein the feedback circuitry includes a multiplexer configured to selectively supply the detected signal edge of the output signal in accordance with a selection signal.
4. The PLL of claim 3 , wherein the multiplexer is configured to supply, in accordance with the selection signal, a supply voltage as the feedback signal when not supplying the detected signal edge.
5. The PLL of claim 3 , wherein the feedback circuitry includes a selection control module configured to detect the signal edge of the output signal and generate the selection signal based on the detected signal edge.
6. The PLL of claim 5 , wherein the selection control module is configured to control a pulse of the selection signal to coincide with the detected signal edge.
7. The PLL of claim 6 , wherein the selection control module controls the pulse of the selection signal to occur only once per cycle of the reference signal.
8. The PLL of claim 6 , wherein the selection control module includes an averaging circuit configured to obtain an average voltage of the output signal in a pulse window determined by the selection control module, and wherein the selection control module is configured to detect the signal edge of the output signal based on the average voltage of the output signal in the pulse window.
9. The PLL of claim 8 , wherein the selection control module is configured to detect the signal edge of the output signal based on a determination of whether the average voltage of the output signal is within a predetermined range of a target voltage.
10. The PLL of claim 9 , wherein the target voltage is a common mode voltage of the output signal.
11. The PLL of claim 1 , wherein the signal edge is a rising edge or a falling edge of the output signal.
12. The PLL of claim 1 , further comprising a charge pump configured to receive phase detection signal and convert the phase detection signal to a control signal.
13. The PLL of claim 12 , further comprising a loop filter configured to output an average of the control signal.
14. A sub-sampling phase locked loop (SSPLL), comprising:
a phase detector configured to
receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency,
sample the feedback signal, and
output a phase detection signal indicative of a phase of the feedback signal;
a voltage controlled oscillator configured to generate an output signal based on the phase detection signal, wherein the output signal has an output frequency greater than the reference frequency;
a selection control module configured to detect a signal edge of the output signal and generate a selection signal based on the detected signal edge; and
a multiplexer configured to selectively supply as the feedback signal, based on the selection signal,
in a first portion of a cycle of the reference signal, the output signal of the voltage controlled oscillator, and
in a second portion of the cycle of the reference signal, a supply voltage.
15. The SSPLL of claim 14 , wherein the selection control module is configured to control a pulse of the selection signal to coincide with the detected signal edge.
16. The SSPLL of claim 15 , wherein the selection control module controls the pulse of the selection signal to occur only once per cycle of the reference signal.
17. The SSPLL of claim 15 , wherein the selection control module includes an averaging circuit configured to obtain an average voltage of the output signal in a pulse window determined by the selection control module, and wherein the selection control module is configured to detect the signal edge of the output signal based on the average voltage of the output signal in the pulse window.
18. The SSPLL of claim 17 , wherein the selection control module is configured to detect the signal edge of the output signal based on a determination of whether the average voltage of the output signal is within a predetermined range of a target voltage.
19. The SSPLL of claim 18 , wherein the target voltage is a common mode voltage of the output signal.
20. The SSPLL of claim 14 , wherein the signal edge is a rising edge or a falling edge of the output signal.