IP Library › Granted Patent US 12,205,824
Granted Patent B2
US 12,205,824 · App. 18/357,038 · Granted Jan 21, 2025

Patterning material including silicon-containing layer and method for semiconductor device fabrication

Inventors: Szu-Ping Tung (Taipei, TW); Chun-Kai Chen (Kaohsiung, TW); Yi-Nien Su (Hsinchu, TW); Tze-Liang Lee (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/3081H01L21/0274H01L21/0332H01L21/0337H01L21/311H01L21/31105H01L21/31116H01L21/31127H01L21/31138H01L21/31144
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Quick Facts
Patent No.
US 12,205,824
App. No.
18/357,038
Granted
Jan 21, 2025
Kind
B2
Abstract

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Claims (43)

1. A method for lithography patterning, comprising:

providing a substrate;

forming a target layer over the substrate;

forming a patterning layer over the target layer, wherein the forming the patterning layer, includes:

using atomic layer deposition (ALD) process to deposit a first layer having an organic composition;

continuing the ALD process to deposit a second layer including over 50 atomic percent of silicon, the second layer deposited directly on the first layer, and

during the ALD process, delivering precursors to the substrate to form a continuous variation in a carbon (C) to silicon (Si) ratio in the first layer and the second layer; and

depositing a patterning layer on the second layer.

2. The method of claim 1 , wherein the target layer includes an interlayer dielectric (ILD) layer formed over the substrate.

3. The method of claim 2 , wherein the patterning layer defines a metallization layer to be formed in the ILD layer; and

recessing an upper surface of the second layer to form a curvilinear upper surface extending between features of the patterning layer.

4. The method of claim 3 , further comprising: trimming a width of the second layer after the recessing the upper surface of the second layer to from a curvilinear upper surface.

5. The method of claim 1 , further comprising:

using the deposited patterning layer to define a metal interconnect line pattern in the target layer.

6. The method of claim 1 , wherein the depositing the second layer includes forming an amorphous silicon (a-Si) layer.

7. The method of claim 6 , wherein the depositing the first layer includes depositing amorphous carbon.

8. The method of claim 1 , further comprising: depositing an adhesion layer between the second layer and the patterning layer.

9. A method for lithography patterning, comprising:

depositing an organic bottom layer over a masking layer disposed over a target layer;

forming a silicon-containing layer over the organic bottom layer using a deposition process providing of precursors delivered toward a surface of the organic bottom layer and chemically modifying the precursors to obtain the silicon-containing layer on the surface, wherein the silicon-containing layer has at least 50% silicon;

forming a patterned resist layer over the silicon-containing layer, the patterned resist layer including a first resist feature;

performing a first etching process to decrease a height of the first resist feature and etch an upper surface of the silicon-containing layer to form a curvilinear surface;

after performing the first etching process, performing a second etching process of the silicon-containing layer to form a first masking feature of the silicon-containing layer having tapered sidewalls and a second masking feature of the silicon-containing layer having tapered sidewalls, wherein an opening extends between the tapered sidewalls of the first and second masking features;

after the second etching process, performing a third etching process of the organic bottom layer under the opening of the second etching process to reduce a height of the silicon-containing layer; and

forming interconnect features according to a pattern defined in the organic bottom layer.

10. The method of claim 9 , further comprising: reducing a width of the patterned bottom organic layer prior to forming interconnect features.

11. The method of claim 9 , wherein the first etching process includes introducing oxygen atoms.

12. The method of claim 11 , wherein the second etching process includes introducing oxygen atoms in a dry etching process.

13. The method of claim 9 , wherein the patterned resist layer is formed directly on the silicon-containing layer.

14. A method for lithography patterning, comprising:

depositing a layer over a substrate;

forming a plurality of features extending from the layer;

forming a patterning layer over the layer and the plurality of features, wherein the forming the patterning layer, includes:

using atomic layer deposition (ALD) process to deposit a first layer having an organic composition interfacing a sidewall of a first feature of the plurality of features;

continuing the ALD process to deposit a second layer including over 50 atomic percent of silicon, wherein the depositing the first layer and the depositing the second layer are performed in-situ, and during the ALD process, delivering precursors to the substrate to form a continuous variation in a carbon (C) to silicon (Si) ratio in the first layer and the second layer; and

depositing a photosensitive layer over the second layer.

15. The method of claim 14 , wherein the plurality of features are mandrels.

16. The method of claim 15 , wherein a height of the first layer is about 1.2 to 4 times a height of the plurality of features.

17. The method of claim 14 , wherein forming the plurality of features includes forming features comprising silicon.

18. The method of claim 14 , wherein the depositing the first layer and the depositing the second layer is performed at room temperature.

19. The method of claim 14 , further comprising:

etching the second layer, wherein after the etching a first thickness of the second layer remains and a second thickness of the first layer remains, wherein a ratio of the first thickness to the second thickness is between 2:1 and 10:1.

20. The method of claim 14 wherein the forming the plurality of features includes forming a first feature and a second feature with a gap extending between the first feature and the second feature, wherein the first layer completely fills the gap.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2023
From: TUNG, SZU-PING; CHEN, CHUN-KAI; LEE, TZE-LIANG; SU, YI-NIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 065453/0574 →
Continuity (3)
Continuation 17213723 · Mar 26, 2021
Provisional Application 63085519 · Sep 30, 2020
Related Publication 20230377897A1 · Nov 23, 2023
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