IP Library Granted Patent US 12,012,326
Granted Patent B2
US 12,012,326 · App. 18/357,784 · Granted Jun 18, 2024

Microelectromechanical microphone with membrane trench reinforcements and method of fabrication

Inventors: Pirmin Hermann Otto Rombach (Kongens Lyngby, DK); Kurt Rasmussen (Herlev, DK); Dennis Mortensen (Bagsvard, DK); Cheng-Yen Liu (Søborg, DK); Morten Ginnerup (Kongens Lyngby, DK); Jan Tue Ravnkilde (Hedehusene, DK); Jotaro Akiyama (Tokyo, JP)
Assignees: TDK Electronics AG; TDK Corporation
B81B3/0051B81C1/00158H04R1/08B81B2201/0257B81B2203/0127B81C2201/053B81C2201/056H04R2201/003
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Quick Facts
Patent No.
US 12,012,326
App. No.
18/357,784
Granted
Jun 18, 2024
Kind
B2
Abstract

In an embodiment, a method for fabricating a Microelectromechanical System (MEMS) microphone includes depositing, on a frontside of a wafer, a first oxide layer over a silicon nitride thin film and over and adjacent the wafer, wherein the silicon nitride thin film is disposed over the wafer, depositing a membrane protection layer over the first oxide layer between a first side of a first cavity formed in the wafer and a second side of a second cavity formed in the wafer, depositing a second oxide layer over and adjacent the membrane protection layer, depositing a first membrane nitride layer over the second oxide layer, depositing a membrane polysilicon layer over the first membrane nitride layer, depositing a second membrane nitride layer over the membrane polysilicon layer, depositing a third oxide layer over the second membrane nitride layer and depositing a fourth oxide layer over the third oxide layer.

Claims (31)

1. A method for fabricating a Microelectromechanical System (MEMS) microphone, the method comprising:

depositing, on a frontside of a wafer, a first oxide layer over a silicon nitride thin film and over and adjacent the wafer, wherein the silicon nitride thin film is disposed over the wafer;

depositing a membrane protection layer over the first oxide layer between a first side of a first cavity formed in the wafer and a second side of a second cavity formed in the wafer;

depositing a second oxide layer over and adjacent the membrane protection layer;

depositing a first membrane nitride layer over the second oxide layer;

depositing a membrane polysilicon layer over the first membrane nitride layer;

depositing a second membrane nitride layer over the membrane polysilicon layer;

depositing a third oxide layer over the second membrane nitride layer depositing a fourth oxide layer over the third oxide layer;

depositing a backplate nitride underlayer over and adjacent the fourth oxide layer and adjacent the third oxide layer;

depositing a first backplate polysilicon layer over and adjacent the backplate nitride underlayer;

depositing a fifth oxide layer at respective portions of the first backplate polysilicon layer;

depositing a second backplate polysilicon layer over the fifth oxide layer and the first backplate polysilicon layer;

depositing metal over the second backplate polysilicon layer and over the first backplate polysilicon layer;

defining a cavity on a backside of the wafer, resulting in a defined structure;

performing a first release of the defined structure;

removing the membrane protection layer;

performing a second release of the defined structure; and

depositing a self-assembled monolayer coating.

2. The method of claim 1 , further comprising:

prior to the depositing the first membrane nitride layer, depositing a nitride reinforcement layer over and adjacent the second oxide layer; and

defining the nitride reinforcement layer.

3. The method of claim 1 , further comprising:

prior to the depositing the second membrane nitride layer, depositing an oxide reinforcement layer; and

defining the oxide reinforcement layer.

4. The method of claim 1 , wherein the depositing the membrane polysilicon layer further comprises defining the membrane polysilicon layer and an area of the membrane polysilicon layer.

5. The method of claim 4 , wherein the defining comprises creating one or more ventilation holes and an active electrode.

6. The method of claim 1 , wherein the depositing the second oxide layer further comprises opening a first lateral etch stop, wherein a corner radius of the first lateral etch stop is more than 100 nanometers.

7. The method of claim 1 , wherein the depositing the fourth oxide layer comprises opening a lateral etch stop comprising etching a first corner radius and a second corner radius.

8. The method of claim 7 , wherein the etching the first corner radius comprises etching the first corner radius to a radius of more than 100 nanometers.

9. The method of claim 7 , wherein the etching the second corner radius comprises etching the second corner radius to a radius of more than 25 nanometers.

10. The method of claim 7 , wherein a step width between the first corner radius and the second corner radius is less than 4 micrometers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2025
From: TDK CORPORATION
To: INVENSENSE, INC.
Reel/Frame 073080/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2024
From: TDK ELECTRONICS AG
To: TDK CORPORATION
Reel/Frame 068289/0950 →