Granted Patent B2

US 12,317,757 · App. 18/357,814 · Granted May 27, 2025

Inventors: Daniel Yohannes (Stamford, CT); Denis Amparo (White Plains, PH); Oleksandr Chernyashevskyy (White Plains, NY); Oleg Mukhanov (Putnam Valley, NY); Mario Renzullo (Yonkers, NY); Andrei Talalaeskii (Mahopac, NY); Igor Vernik (Yorktown Heights, NY); John Vivalda (Poughkeepsie, NY); Jason Walter (Trumbull, CT)

Assignee: SeeQC, Inc.

H10N60/815H01L24/05H01L24/13H01L24/81H10N60/0912H10N60/12H01L2224/0401H01L2224/05179H01L2224/13083H01L2224/13109H01L2224/13147H01L2224/13166H01L2224/13179H01L2224/8109H01L2224/8112H01L2224/81203H01L2924/04941H01L2924/0495

Abstract

Claims (37)

1. A superconducting multi-chip module, comprising:

a first chip comprising a plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements;

a second chip comprising a plurality of Josephson junctions configured to generate single-flux-quantum pulses to control and read out the qubits, sensors, or memory elements on the first chip; and

a plurality of alignment posts and deformable metal contacts configured to form electrical bump bonds coupling the first chip and the second chip, the electrical bump bonds being formed by pressure on the deformable metal contacts below a melting temperature of the deformable metal,

wherein the bonds remain stable with respect to repeated cycling between room temperature and a cryogenic operating temperature of the plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements.

2. The superconducting multi-chip module of claim 1 , wherein the first chip comprises a quantum computing circuit.

3. The superconducting multi-chip module of claim 2 , wherein the first chip comprises transmon qubits.

4. The superconducting multi-chip module of claim 2 , wherein the first chip is configured to operate at a temperature less than 1 K.

5. The superconducting multi-chip module of claim 2 , wherein the alignments posts are not superconducting at an operating temperature of the quantum computing circuit, and serve to thermalize excited quasiparticles in the quantum computing circuit.

6. The superconducting multi-chip module of claim 1 , wherein the first chip comprises a cryogenic imaging array, and the second chip comprises a digital readout system matched to the cryogenic imaging array.

7. The superconducting multi-chip module of claim 6 , wherein the cryogenic imaging array comprises a plurality of SQUIDs.

8. The superconducting multi-chip module of claim 6 , wherein the cryogenic imaging array comprises an electromagnetic imaging sensor for astronomy or high-energy physics.

9. The superconducting multi-chip module of claim 1 , wherein the first chip comprises a cryogenic memory array, and the second chip comprises a superconducting digital processor.

10. The superconducting multi-chip module of claim 1 , wherein the second chip is mounted in a flip-chip configuration on the first chip.

11. The superconducting multi-chip module of claim 1 , wherein at least one of the first chip and the second chip comprises through-chip superconducting vias, configured to bond without direct contact of the circuits on the first chip and the second chip.

12. The superconducting multi-chip module of claim 1 , wherein the deformable metal contact comprises indium and the alignment posts comprise at least one of copper, gold, and silver.

13. The superconducting multi-chip module of claim 1 , further comprising a superconducting diffusion-stopping layer deposited between the alignment posts and the deformable metal contact.

14. The superconducting multi-chip module of claim 13 , wherein the superconducting diffusion-stopping layer comprises niobium nitride or titanium nitride.

15. The superconducting multi-chip module of claim 1 , wherein the second chip comprises Josephson junctions comprising at least one of niobium, niobium nitride, niobium-titanium, aluminum, molybdenum, and titanium.

16. The superconducting multi-chip module of claim 1 , wherein the plurality of alignment posts and deformable metal contacts comprise thousand of bonds, each less than 30 micrometers in diameter.

17. The superconducting multi-chip module of claim 1 , wherein the electrical bump bonds are strengthened with epoxy.

18. The superconducting multi-chip module of claim 1 , where the deformable metal contacts have a critical current of at least 10 mA at an operating temperature of less than 3 K.

19. A superconducting multi-chip module, comprising:

a first chip comprising a plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements;

a second chip comprising a plurality of Josephson junctions configured to generate single-flux-quantum pulses to control and read out the qubits, sensors, or memory elements on the first chip; and

a plurality of bonds on alignment posts,

wherein the plurality of bonds each comprise a deformable metal bonded under pressure at a temperature under 150° C. without melting of the deformable metal,

wherein the bonds remain stable with respect to repeated cycling between room temperature and a cryogenic operating temperature of the a plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements.

20. The superconducting multi-chip module of claim 19 , wherein the chips are reversibly unbonded and rebonded without damage to the first chip or the second chip.

21. The superconducting multi-chip module of claim 19 , wherein the plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements comprise a plurality of transmon qubits configured to operate at a temperature less than 1 K; and the alignments posts are not superconducting at 1 K, and serve to thermalize excited quasiparticles in the first chip.

22. A method of forming a superconducting multi-chip module, comprising:

providing a first chip comprising a plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements, and having a plurality of first alignment posts capped with a deformable metal;

providing a second chip comprising a plurality of Josephson junctions configured to generate single-flux-quantum pulses to control and read out the qubits, sensors, or memory elements on the first chip, and having a plurality of second alignment posts capped with a deformable metal;

aligning the first alignment posts with the second alignment posts; and

compressing the first chip against the second chip, with the first alignment posts with the second alignment posts aligned, at a temperature of less than 150° C., to form a bond

wherein the plurality of electrically conductive mechanical bonds, each comprise a deformable metal bonded under pressure at a temperature under 150° C. without melting of the deformable metal, and

wherein the plurality of electrically conductive mechanical bonds remain stable with respect to repeated cycling between room temperature and a cryogenic operating temperature of the a plurality of coupled superconducting qubits, superconducting electromagnetic sensors, or cryogenic memory elements.

Assignments (2)

Continuity (4)

References Cited (400)