Biased conditional instruction prediction
A processor may include a conditional instruction prediction tracking circuit. During fetch of a conditional instruction from memory to an instruction cache of the processor, the conditional instruction prediction tracking circuit may predict whether the conditional instruction is biased. Responsive to a prediction that the conditional instruction is biased, the conditional instruction prediction tracking circuit may cause the conditional instruction to be executed according to the predicted bias. Sometimes the conditional prediction tracking circuit may cause the conditional instruction to be re-coded such that it may be executed as an unconditional instruction.
1. A processor, comprising:
a prefetch circuit configured to fetch instructions including a conditional instruction from memory to an instruction cache; and
a prediction circuit configured to:
predict, during fetch of the conditional instruction to the instruction cache, whether the conditional instruction is biased to a condition outcome affecting a data flow for the instruction; and
responsive to a prediction that the conditional instruction is biased, cause the conditional instruction to be executed according to the predicted bias of the conditional instruction.
2. The processor of claim 1 , wherein to predict whether the conditional instruction is biased, the prediction circuit is configured to:
identify a prediction value for the conditional instruction from a prediction table; and
provide the prediction based on the prediction value for the conditional instruction.
3. The processor of claim 2 , wherein the prediction table comprises one or more entries corresponding respectively to one or more conditional instructions, and wherein an entry for a particular conditional instruction comprises:
an index associated with the particular conditional instruction; and
a prediction value for the particular conditional instruction, wherein the prediction value is one of:
a first value representing that no prediction has been provided for the particular conditional instruction;
a second value representing that the particular conditional instruction is biased false;
a third value representing that the particular conditional instruction is biased true; or
a fourth value representing that the particular conditional instruction is not biased.
4. The processor of claim 3 , wherein the index associated with the particular conditional instruction is generated based on hashing an address associated with the particular conditional instruction.
5. The processor of claim 3 , wherein to generate the entry for the conditional instruction, the prediction circuit is configured to:
determine whether the prediction table includes an entry corresponding to the conditional instruction;
responsive to a determination that the prediction table does not include the entry corresponding to the conditional instruction:
set the prediction value for the conditional instruction to the first value;
obtain a resolution result of the condition of the conditional instruction; and
update the prediction value from the first value to the second or third value based on the resolution result; and
responsive to a determination that the prediction table includes the entry for the conditional instruction and the prediction value of the entry is the second or third value:
obtain a resolution result of the condition of the conditional instruction;
determine whether the prediction of the resolution instruction matches the resolution result; and
responsive to a determination that the prediction does not match the resolution result, update the prediction value from the second or third value to the fourth value; and
responsive to a determination that the prediction table includes the entry for the conditional instruction and the prediction value of the entry is the fourth value, maintain the prediction value as the fourth value.
6. The processor of claim 5 , wherein to update the prediction value from the first value to the second or third value based on the resolution result, the prediction circuit is configured to:
generate a prediction value for the conditional instruction in a buffer based on the resolution result of the condition of the conditional instruction;
determine whether the conditional instruction becomes non-speculative; and
responsive to the determination that the conditional instruction becomes non-speculative, update the prediction value for the conditional instruction in the prediction table to the second or third value according to the prediction value in the buffer.
7. The processor of claim 5 , wherein responsive to a determination that the prediction does not match the resolution result, the prediction circuit is configured to cause the conditional instruction to be re-fetched by the prefetch circuit from the memory to the instruction cache.
8. The processor of claim 1 , wherein the conditional instruction is a conditional select instruction, and wherein responsive to the prediction that the conditional select instruction is biased, the prediction circuit is configured to cause the conditional select instruction to be re-coded to a move instruction.
9. The processor of claim 1 , wherein the conditional instruction is one of a conditional select instruction, a conditional set instruction, a conditional set mask instruction, a conditional increment instruction, a conditional invert instruction, a conditional negate instruction, a conditional select increment instruction, a conditional select invert instruction, or a conditional select negate instruction.
10. The processor of claim 1 , wherein the instructions fetched by the prefetch circuit includes a conditional branch instruction, and wherein the prediction circuit is configured to:
predict, during fetch of the conditional branch instruction to the instruction cache, whether the conditional branch instruction is biased using the same prediction table as the conditional instruction.
11. A system, comprising:
one or more processors individually comprising an instruction cache;
memory configured to store instructions; and
a display configured to display images;
wherein the processors individually comprise:
a prefetch circuit configured to fetch at least some of the instructions from the memory to the instruction cache of the individual processor, wherein the at least some instructions include a conditional instruction; and
a prediction circuit configured to:
predict, during fetch of the conditional instruction to the instruction cache, whether the conditional instruction is biased to a condition outcome affecting a data flow for the instruction; and
responsive to a prediction that the conditional instruction is biased, cause the conditional instruction to be executed according to the predicted bias of the conditional instruction.
12. The system of claim 11 , wherein to predict whether the conditional instruction is biased, the prediction circuit is further configured to:
identify a prediction value for the conditional instruction from a prediction table; and
provide the prediction based on the prediction value for the conditional instruction.
13. The system of claim 12 , wherein the prediction table comprises one or more entries corresponding respectively to one or more conditional instructions, and wherein an entry for a particular conditional instruction comprises:
an index associated with the particular conditional instruction; and
a prediction value for the particular conditional instruction, wherein the prediction value is one of:
a first value representing that no prediction has been provided for the particular conditional instruction;
a second value representing that the particular conditional instruction is biased false;
a third value representing that the particular conditional instruction is biased true; or
a fourth value representing that the particular conditional instruction is not biased.
14. The system of claim 13 , wherein the index associated with the particular conditional instruction is generated based on hashing an address associated with the particular conditional instruction.
15. The system of claim 13 , wherein to generate the entry for the conditional instruction, the prediction circuit is configured to:
determine whether the prediction table includes an entry corresponding to the conditional instruction;
responsive to a determination that the prediction table does not include the entry corresponding to the conditional instruction:
set the prediction value for the conditional instruction to the first value;
obtain a resolution result of the condition of the conditional instruction; and
update the prediction value from the first value to the second or third value based on the resolution result; and
responsive to a determination that the prediction table includes the entry for the conditional instruction and the prediction value of the entry is the second or third value:
obtain a resolution result of the condition of the conditional instruction;
determine whether the prediction of the resolution instruction matches the resolution result; and
responsive to a determination that the prediction does not match the resolution result, update the prediction value from the second or third value to the fourth value; and
responsive to a determination that the prediction table includes the entry for the conditional instruction and the prediction value of the entry is the fourth value, maintain the prediction value as the fourth value.
16. The system of claim 15 , wherein to update the prediction value from the first value to the second or third value based on the resolution result, the prediction circuit is configured to:
generate a prediction value for the conditional instruction in a buffer based on the resolution result of the condition of the conditional instruction;
determine whether the conditional instruction becomes non-speculative; and
responsive to the determination that the conditional instruction becomes non-speculative,
update the prediction value for the conditional instruction in the prediction table to the second or third value according to the prediction value in the buffer.
17. The system of claim 11 , wherein the conditional instruction is a conditional select instruction, and wherein responsive to the prediction that the conditional select instruction is biased, the prediction circuit is configured to cause the conditional select instruction to be re-coded to a move instruction.
18. A method, comprising:
fetching instructions, including a conditional instruction, by a prefetch circuit of a processor from memory to an instruction cache;
predicting, during fetching of the conditional instruction to the instruction cache, by a bias prediction circuit of the processor whether the conditional instruction is biased to a condition outcome affecting a data flow for the instruction; and
responsive to a prediction that the conditional instruction is biased, executing, by the processor, the conditional instruction according to the predicted bias of the conditional instruction.
19. The method of claim 18 , wherein predicting whether the conditional instruction is biased comprises:
identifying a prediction value for the conditional instruction from a prediction table; and
providing the prediction based on the prediction value for the conditional instruction;
wherein the prediction table comprises one or more entries corresponding respectively to one or more conditional instructions, and wherein an entry for a particular conditional instruction comprises:
an index associated with the particular conditional instruction; and
a prediction value for the particular conditional instruction, wherein the prediction value is one of:
a first value representing that no prediction has been provided for the particular conditional instruction;
a second value representing that the particular conditional instruction is biased false;
a third value representing that the particular conditional instruction is biased true; or
a fourth value representing that the particular conditional instruction is not biased.
20. The method of claim 18 , wherein the conditional instruction is a conditional select instruction, and wherein executing the conditional instruction according to the predicted bias of the conditional instruction comprises re-coding the conditional select instruction to a move instruction.