Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes

1. A branch predictor, comprising:

a block address useable to access a block of instruction bytes of an instruction cache of a processor;

a first byte offset within the block of instruction bytes;

a second byte offset within the block of instruction bytes;

hashing logic that hashes a branch pattern and a first address formed from the block address and the first byte offset to generate a first index and that hashes the branch pattern and a second address formed from the block address and the second byte offset to generate a second index;

a conditional branch predictor that receives the first and second indexes and in response provides respective first and second direction predictions of first and second conditional branch instructions in the block of instruction bytes; and

a branch target address cache (BTAC) that provides the first and second byte offsets to the hashing logic in response to the block address.

2. The branch predictor of claim 1 , further comprising:

wherein the BTAC, in response to the block address, also provides first and second branch target address predictions corresponding to the first and second byte offsets; and

wherein the branch predictor statically associates the first direction prediction provided by the conditional branch predictor with the first branch target address prediction provided by the BTAC and statically associates the second direction prediction provided by the conditional branch predictor with the second branch target address prediction provided by the BTAC.

3. The branch predictor of claim 1 , further comprising:

wherein the first and second byte offsets each are N bits, wherein N is log.sub.2Q, wherein Q is a number of instruction bytes in the block of instruction bytes provided by the instruction cache in response to the block address.

4. The branch predictor of claim 1 , further comprising:

wherein the conditional branch predictor is updated using a correctly resolved address of a conditional branch instruction executed by the processor.

5. The branch predictor of claim 1 , further comprising:

wherein the first byte offset has a first predetermined value and the second byte offset has a second predetermined value, wherein the first and second predetermined values are different.

6. The branch predictor of claim 1 , further comprising:

in response to the block address, the BTAC provides a branch target address prediction and a corresponding byte offset for each of the first and second conditional branch instructions;

wherein the branch predictor determines which of the byte offsets provided by the BTAC has a smaller value and which has a larger value; and

wherein the branch predictor dynamically associates the first direction prediction provided by the conditional branch predictor with the branch target address prediction whose corresponding byte offset provided by the BTAC has the smaller value and dynamically associates the second direction prediction provided by the conditional branch predictor with the branch target address prediction whose corresponding byte offset provided by the BTAC has the larger value.

7. The branch predictor of claim 6 , further comprising:

wherein the BTAC is accessed by the block address and the conditional branch predictor is accessed by the first and second indexes within a same clock cycle.

8. The branch predictor of claim 5 , further comprising:

wherein the conditional branch predictor is updated using one of the first and second indexes generated by the hashing logic.

9. The branch predictor of claim 1 , further comprising:

wherein the conditional branch predictor comprises a memory having first and second ports that respectively receive the first and second indexes and respectively provide the first and second direction predictions.

10. The branch predictor of claim 9 , further comprising:

wherein the conditional branch predictor comprises a plurality of memories, wherein each memory of the plurality of memories has first and second ports that receive a respective pair of first and second indexes and provide respective first and second direction predictions; and

wherein the hashing logic hashes a different length of the branch pattern and the first/second address formed from the block address and the first/second byte offset to generate the first/second indexes for each of the plurality of memories.

11. The branch predictor of claim 1 , further comprising:

wherein the hashing logic comprises combinatorial logic that receives the block address, the branch pattern, the first offset and the second offset and in response generates the first and second indexes.

12. A method for operating a branch predictor, the method comprising:

using a block address to access a block of instruction bytes of an instruction cache of a processor;

providing first and second byte offsets within the block of instruction bytes;

hashing a branch pattern and a first address formed from the block address and the first byte offset to generate a first index and hashing the branch pattern and a second address formed from the block address and the second byte offset to generate a second index;

providing, by a conditional branch predictor, respective first and second direction predictions of first and second conditional branch instructions in the block of instruction bytes in response to receiving the first and second indexes; and

providing, by a branch target address cache (BTAC), the first and second byte offsets in response to the block address.

13. The method of claim 12 , further comprising:

providing, also by the BTAC in response to the block address, first and second branch target address predictions corresponding to the first and second byte offsets; and

statically associating the first direction prediction provided by the conditional branch predictor with the first branch target address prediction provided by the BTAC and statically associating the second direction prediction provided by the conditional branch predictor with the second branch target address prediction provided by the BTAC.

14. The method of claim 12 , further comprising:

updating the conditional branch predictor using a correctly resolved address of a conditional branch instruction executed by the processor.

15. The method of claim 12 , further comprising:

wherein the first byte offset has a first predetermined value and the second byte offset has a second predetermined value, wherein the first and second predetermined values are different.

16. The method of claim 12 , further comprising:

providing, by the BTAC in response to the block address, a branch target address prediction and a corresponding byte offset for each of the first and second conditional branch instructions;

determining which of the byte offsets provided by the BTAC has a smaller value and which has a larger value; and

dynamically associating the first direction prediction provided by the conditional branch predictor with the branch target address prediction whose corresponding byte offset provided by the BTAC has the smaller value and dynamically associating the second direction prediction provided by the conditional branch predictor with the branch target address prediction whose corresponding byte offset provided by the BTAC has the larger value.

17. The method of claim 12 , further comprising:

updating the conditional branch predictor using one of the first and second indexes generated by the hashing logic.

18. The method of claim 12 , further comprising:

wherein the conditional branch predictor comprises a memory having first and second ports that respectively receive the first and second indexes and respectively provide the first and second direction predictions.

19. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a branch predictor, the computer usable program code comprising:

first program code for specifying a block address useable to access a block of instruction bytes of an instruction cache of a processor;

second program code for specifying a first byte offset within the block of instruction bytes;

third program code for specifying a second byte offset within the block of instruction bytes;

fourth program code for specifying hashing logic that hashes a branch pattern and a first address formed from the block address and the first byte offset to generate a first index and that hashes the branch pattern and a second address formed from the block address and the second byte offset to generate a second index; and

fifth program code for specifying a conditional branch predictor that receives the first and second indexes and in response provides respective first and second direction predictions of first and second conditional branch instructions in the block of instruction bytes;

wherein a branch target address cache (BTAC) provides the first and second byte offsets to the hashing logic in response to the block address.