Semiconductor devices with backside via and methods thereof
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.
1. A method, comprising:
receiving a workpiece comprising:
a gate structure over a channel region protruding from a substrate, and
a first source/drain feature and a second source/drain feature coupled to the channel region;
forming a first dielectric structure directly over the first source/drain feature and the second source/drain feature, a top surface of the first dielectric structure is coplanar with a top surface of the gate structure;
forming a second dielectric structure on the first dielectric structure;
forming a dielectric feature extending through the second dielectric structure and the first dielectric structure to direct contact the first source/drain feature, a composition of the dielectric feature is different from compositions of the first and second dielectric structures;
forming a first source/drain contact disposed directly under the first source/drain feature and electrically coupled to the first source/drain feature; and
forming a second source/drain contact extending through the second dielectric structure and the first dielectric structure to electrically couple to the second source/drain feature.
2. The method of claim 1 , wherein the forming of the first dielectric structure comprises:
conformally depositing a contact etch stop layer over the workpiece;
forming an interlayer dielectric layer on the contact etch stop layer; and
performing a planarization process to remove portions of the contact etch stop layer and interlayer dielectric layer formed over the gate structure.
3. The method of claim 1 , wherein the workpiece further comprises a gate spacer extending along a sidewall surface of the gate structure, wherein the dielectric feature is in direct contact with a top surface of the gate spacer.
4. The method of claim 1 , wherein the channel region comprises a vertical stack of alternating channel layers and sacrificial layers, the method further comprises:
after the forming of the first dielectric structure, selectively remove the gate structure and selectively removing the sacrificial layers; and
forming a gate stack to wrap around each of the channel layers.
5. The method of claim 4 , further comprising: after the forming of the dielectric feature, forming a gate via extending through the second dielectric structure to electrically couple to the gate stack.
6. The method of claim 5 , wherein the gate via is vertically overlapped with the dielectric feature.
7. The method of claim 5 , wherein, in a top view, a distance between the gate via and the second source/drain contact is greater than a distance between the gate via and the dielectric feature.
8. The method of claim 1 , wherein a contact area between the dielectric feature and the first source/drain feature is greater than a contact area between the second source/drain contact and the second source/drain feature.
9. The method of claim 1 ,
wherein the workpiece further comprises a semiconductor feature disposed immediately under the first source/drain feature and in the substrate, and the forming of the first source/drain contact comprises:
planarizing the substrate to expose a bottom surface of the semiconductor feature;
replacing the substrate with a dielectric material layer;
selectively removing the semiconductor feature to form a backside opening;
forming a silicide layer in the backside opening and in direct contact with the first source/drain feature; and
depositing a conductive material in the backside opening to form the first source/drain contact.
10. The method of claim 1 , wherein a top surface of the dielectric feature spans a first width, and a top surface of the second source/drain contact spans a second width less than the first width.
11. A method, comprising:
forming a first dielectric structure over a first source/drain feature formed in a first source/drain recess;
forming a second dielectric structure over the first dielectric structure;
patterning the first dielectric structure and the second dielectric structure to form a first opening exposing an entirety of a top surface of the first source/drain feature;
forming a dielectric feature in the first opening; and
forming a first source/drain contact disposed directly under the first source/drain feature.
12. The method of claim 11 ,
wherein the patterning of the first dielectric structure and the second dielectric structure further forms a second opening exposing a portion of a top surface of a second source/drain feature, and the method further comprises:
forming a second source/drain contact in the second opening.
13. The method of claim 11 , wherein the forming of the first source/drain contact comprises:
after forming the first source/drain recess, performing an etching process to vertically extend the first source/drain recess;
forming a semiconductor plug in a lower portion of the vertically extended first source/drain recess, wherein the first source/drain feature is formed in an upper portion of the vertically extended first source/drain recess and on the semiconductor plug; and
after the forming of the dielectric feature, replacing the semiconductor plug with the first source/drain contact.
14. The method of claim 11 , further comprising:
after the forming of the dielectric feature, forming a third dielectric structure on the second dielectric structure;
forming a gate via extending through the third dielectric structure and the second dielectric structure to electrically couple to a gate structure disposed adjacent to the dielectric feature.
15. The method of claim 14 , wherein the gate via is partially landed on the dielectric feature.
16. The method of claim 14 , wherein, in a top view, a distance between the gate via and the first source/drain contact is greater than a distance between the gate via and the dielectric feature.
17. A method, comprising:
receiving a workpiece comprising:
an active region over a substrate;
a gate structure disposed over a channel region of the active region,
a first source/drain feature disposed over a first source/drain region of the active region and disposed over a semiconductor plug in the substrate;
a second source/drain feature disposed over a second source/drain region of the active region, and
a first dielectric layer comprising a first portion disposed directly over the first source/drain feature and a second portion disposed directly over the second source/drain feature;
selectively removing the first portion of the first dielectric layer to form an isolation feature opening that exposes the first source/drain feature;
forming an isolation feature in the isolation feature opening, a composition of the isolation feature being different than a composition of the first dielectric layer; and
replacing the semiconductor plug with a backside source/drain contact.
18. The method of claim 17 , further comprising:
forming a source/drain contact opening through the first dielectric layer to expose the second source/drain feature;
forming a source/drain contact in the source/drain contact opening;
forming a second dielectric layer over the first dielectric layer;
forming a via opening through the first and the second dielectric layer to expose the gate structure; and
forming a contact via in the via opening and in direct contact with the gate structure,
wherein a distance between the contact via and the source/drain contact is greater than a distance between the contact via and the isolation feature.
19. The method of claim 18 ,
wherein the workpiece further comprises:
a first gate spacer disposed along a first sidewall of the gate structure and laterally adjacent to the isolation feature, and
a second gate spacer disposed along a second sidewall of the gate structure and laterally adjacent to the source/drain contact,
wherein the via opening further exposes at least a portion of the first gate spacer, and the contact via is further in direct contact with the first gate spacer.
20. The method of claim 18 ,
wherein the via opening further exposes a portion of the isolation feature, and the contact via is further in direct contact with the isolation feature.