Memory device
According to one embodiment, a memory device includes a first substrate and a second substrate. The first substrate is provided with a first circuit layer on a front surface. The first circuit layer includes a CMOS circuit. The second substrate has a front surface that faces the first substrate. The second substrate is provided with a second circuit layer on the front surface contacting the first circuit layer. The second substrate includes a memory circuit and transistors of a silicon-on-insulator (SOI) structure.
1 . A memory device, comprising:
a first substrate with a first circuit layer on a front surface, the first circuit layer including a CMOS circuit;
a second substrate having a front surface facing the front surface of the first substrate, the second substrate being provided with a second circuit layer on the front surface contacting the first circuit layer, and the second circuit layer including a memory circuit and transistors of a silicon-on-insulator (SOI) structure; and
a first insulator layer on a back surface of the second substrate, wherein
the second substrate includes:
a first insulating member in contact with the first insulator layer and dividing the second substrate into regions including well regions in each of which a transistor is formed;
the second circuit layer includes:
a second insulator layer on the front surface of the second substrate, and
a gate electrode of one of the transistors facing one of the well regions with the second insulator layer being between the gate electrode and the one of the well regions; and
the transistors are separated into islands by the first insulating member.
2 . The memory device according to claim 1 , wherein transistors in the CMOS circuit are different from the island-shaped insulating SOI structure of the transistors in the well regions of the second substrate.
3 . The memory device according to claim 1 , wherein the second circuit layer further includes:
a plurality of contacts extending in a first direction and having lower surfaces at the same height, the plurality of contacts including a contact coupled to the one of the well regions and a contact coupled to the gate electrode.
4 . The memory device according to claim 1 , wherein
the second substrate includes a first impurity diffusion region including an N-type impurity, the first impurity diffusion region extending from the front surface to the back surface of the second substrate,
the second circuit layer further includes:
a first semiconductor layer below the first impurity diffusion region in the first direction,
a second semiconductor layer under the first semiconductor layer in the first direction,
a plurality of word lines stacked in the first direction below the second semiconductor layer, and
a memory pillar extending in the first direction and intersecting the plurality of word lines to form memory cells,
the first semiconductor layer and the second semiconductor layer function a source line in the memory circuit, and
the thickness of the second semiconductor layer along the first direction is substantially equal to the thickness of the gate electrode along the first direction.
5 . The memory device according to claim 4 , wherein the height of a lower surface of the second semiconductor layer is substantially the same as the height of a lower surface of the gate electrode.
6 . The memory device according to claim 4 , wherein each of the plurality of word lines is electrically connected to the CMOS circuit via one of the transistors of the second circuit layer.
7 . The memory device according to claim 4 , wherein
the second circuit layer further includes a bit line extending in a second direction intersecting with the first direction, the bit line being below the plurality of word lines in the first direction and electrically connected to the memory pillar, and
the bit line is also being electrically connected to the CMOS circuit via at least one of the transistors of the second circuit layer.
8 . The memory device according to claim 4 , further comprising:
a first conductor layer on the back surface of the second substrate, wherein
the second substrate includes a second impurity diffusion region including an N-type impurity from the front surface to the back surface of the second substrate, and
the first conductor layer is electrically connected to the CMOS circuit through the second impurity diffusion region.
9 . The memory device according to claim 8 , wherein the first conductor layer is used to supply a power supply voltage to the CMOS circuit.
10 . The memory device according to claim 8 , wherein the second impurity diffusion region is insulated and spaced from the first impurity diffusion region.
11 . The memory device according to claim 4 , wherein
the memory pillar includes a third semiconductor layer extending in the first direction, and
the first semiconductor layer is in contact with the third semiconductor layer via a side surface of the memory pillar.
12 . The memory device according to claim 1 , wherein
the second substrate is provided with a plurality of memory cell arrays, and
the plurality of memory cell arrays includes a first memory cell array with a memory circuit connected to the CMOS circuit via one of the transistors of the SOI structure and a second memory cell array with a memory circuit connected to the CMOS circuit by none of the transistors of the SOI structure.
13 . The memory device according to claim 12 , wherein
the first and second circuit layers include:
a first control circuit configured to control the first memory cell array; and
a second control circuit configured to control the second memory cell array,
the first control circuit has a first portion on the first substrate and a second portion on the second substrate,
the second control circuit is on the first substrate, and
the total area of the second control circuit and the first portion of the first control circuit is the same as the total area of the first memory cell array, the second memory cell array, and the second portion of the first control circuit.
14 . The memory device according to claim 13 , wherein the area of the first memory cell array is different from the area of the second memory cell array.
15 . The memory device according to claim 1 , wherein the transistors are high-voltage transistors.
16 . The memory device according to claim 1 , wherein the CMOS circuit is not above the second substrate.
17 . The memory device according to claim 1 , wherein
the first circuit layer includes a second conductor layer,
the second circuit layer includes a third conductor layer in contact with the second conductor layer,
the second conductor layer and the third conductor layer are connected in series between the transistors and the CMOS circuit,
the second conductor layer has a reverse taper shape, and
the third conductor layer has a taper shape.
18 . A memory device, comprising:
a first substrate with a first circuit layer on a front surface, the first circuit layer including a CMOS circuit; and
a second substrate having a front surface facing the front surface of the first substrate in a first direction, the second substrate being provided with a second circuit layer on the front surface contacting the first circuit layer, and the second circuit layer including a first-type transistor and a memory circuit, wherein
the second substrate includes:
a first impurity diffusion region including N-type impurities, the first impurity diffusion region extending from the front surface to a back surface of the second substrate, and
a well region insulated and spaced from the first impurity diffusion region,
the second circuit layer includes:
a first semiconductor layer below the first impurity diffusion region,
a second semiconductor layer under the first semiconductor layer,
a plurality of word lines stacked in the first direction below the second semiconductor layer,
a memory pillar extending in the first direction and intersecting with the plurality of word lines to form memory cell transistors, and
a gate electrode of the first-type transistor facing the well region, the well region functioning as an active region of the first-type transistor, the first-type transistor being different from the memory cell transistor,
the first impurity diffusion region, the first semiconductor layer, and the second semiconductor layer function as a source line in the memory circuit,
the well region is at a position corresponding to the first impurity diffusion region in the first direction, and
the gate electrode is at a position corresponding to the second semiconductor layer in the first direction.
19 . The memory device according to claim 18 , wherein a first portion of the memory circuit is electrically connected to the CMOS circuit via the first-type transistor.
20 . A memory device, comprising:
a first substrate with a first circuit layer on a front surface, the first circuit layer including a CMOS circuit; and
a second substrate having a front surface facing the front surface of the first substrate, the second substrate being provided with a second circuit layer on the front surface contacting the first circuit layer, and the second circuit layer including a memory circuit and transistors of a silicon-on-insulator (SOI) structure, wherein
the second substrate is provided with a plurality of memory cell arrays,
the plurality of memory cell arrays includes a first memory cell array with a memory circuit connected to the CMOS circuit via one of the transistors of the SOI structure and a second memory cell array with a memory circuit connected to the CMOS circuit by none of the transistors of the SOI structure,
the first and second circuit layers include:
a first control circuit configured to control the first memory cell array; and
a second control circuit configured to control the second memory cell array,
the first control circuit has a first portion on the first substrate and a second portion on the second substrate,
the second control circuit is on the first substrate, and
the total area of the second control circuit and the first portion of the first control circuit is the same as the total area of the first memory cell array, the second memory cell array, and the second portion of the first control circuit.