Memory device structure and fabrication method

1 . A method for forming a three-dimensional (3D) memory device, comprising:

forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one stair structure region for forming a stair structure, including: forming the plurality of memory cells in the at least one cell region, and forming the stair structure in the at least one stair structure region;

forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one stair structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region, including: forming HV circuits of a string driver in the at least one string driver region, and forming HV circuits of page buffers in the at least one page buffer HV circuit region;

forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region, including forming low-voltage (LV) circuits of the page buffers in the at least one page buffer region; and

forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer, wherein the array wafer, the first CMOS wafer, and the second CMOS wafer are stacked together,

wherein the forming the 3D memory device further comprises: forming an isolating layer over the first substrate; forming at least one through substrate contact penetrating the first substrate; and forming one or more array pads in contact with the at least one through substrate contact,

wherein the forming the second CMOS wafer further comprises:

bonding the third substrate to the first CMOS wafer; and

forming the LV circuits of the page buffer on the third substrate and in the at least one page buffer region,

wherein the first CMOS wafer and the second CMOS wafer form a bonded first CMOS wafer and second CMOS wafer,

wherein the forming the 3D memory device further comprises:

bonding the array wafer to the bonded first CMOS wafer and second CMOS wafer at a bonding interface, such that a top surface of the array wafer is bonded to a top surface of the second CMOS wafer, and the first substrate is at top of the bonded array wafer and second CMOS wafer.

2 . The method according to claim 1 , wherein

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer;

the at least one string driver region is a single center portion of the first CMOS wafer;

the at least one page buffer HV circuit region are four side portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two side portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes four through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the four side portions of first CMOS wafer and the LV circuits of the page buffers in the two side portions of the second CMOS wafer.

3 . The method according to claim 1 , wherein

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer;

the at least one string driver region are two staggered regions at a center portion of the first CMOS wafer;

the at least one page buffer HV circuit region are two side portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two side portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two side portions of first CMOS wafer and the LV circuits of the page buffers in the two side portions of the second CMOS wafer.

4 . The method according to claim 1 , wherein:

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer;

the at least one string driver region are two side portions of the first CMOS wafer;

the at least one page buffer HV circuit region are two center portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region is one center portion of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two center portions of first CMOS wafer and the LV circuits of the page buffers in the one center portion of the second CMOS wafer.

5 . The method according to claim 1 , wherein:

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer;

the at least one string driver region are two side portions of the first CMOS wafer;

the at least one page buffer HV circuit region are two center portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two center portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two center portions of first CMOS wafer and the LV circuits of the page buffers in the two center portions of the second CMOS wafer.

6 . The method according to claim 1 , wherein:

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer; and

the second CMOS wafer further includes a controller in memory (CIM) structure formed in at least one CIM region of the third substrate to provide control functions for the 3D memory device,

wherein the at least one CIM region are two side portions of the second CMOS wafer.

7 . The method according to claim 1 , wherein:

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer; and

the second CMOS wafer further includes a controller in memory (CIM) structure formed in at least one CIM region of the third substrate to provide control functions for the 3D memory device,

wherein the at least one CIM region is a lower center portion of the second CMOS wafer.

8 . A three-dimensional (3D) memory device, comprising:

an array wafer including a first substrate having at least one cell region and at least one stair structure region, a plurality of memory cells formed in the at least one cell region, and a stair structure formed in the at least one stair structure region;

a first complementary metal-oxide-semiconductor (CMOS) wafer including a second substrate having at least one string driver region corresponding to the at least one stair structure region and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region, HV circuits of a string driver formed in the at least one string driver region, and HV circuits of page buffers formed in the at least one page buffer HV circuit region; and

a second CMOS wafer including a third substrate having at least one page buffer region corresponding to the at least one cell region, and low-voltage (LV) circuits of the page buffers formed in the at least one page buffer region;

wherein the array wafer, the first CMOS wafer, and the second CMOS wafer are stacked together, and

wherein the 3D memory device further comprises: an isolating layer formed over the first substrate; at least one through substrate contact penetrating the first substrate; and one or more array pads in contact with the at least one through substrate contact,

wherein:

the third substrate is combined with the first CMOS wafer;

the LV circuits of the page buffer are formed on the third substrate and in the at least one page buffer region;

the first CMOS wafer and the second CMOS wafer form a bonded first CMOS wafer and second CMOS wafer; and

the array wafer is bonded to the bonded first CMOS wafer and second CMOS wafer at a bonding interface.

9 . The 3D memory device according to claim 8 , wherein

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer;

the at least one string driver region is a single center portion of the first CMOS wafer;

the at least one page buffer HV circuit region are four side portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two side portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes four through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the four side portions of first CMOS wafer and the LV circuits of the page buffers in the two side portions of the second CMOS wafer.

10 . The 3D memory device according to claim 8 , wherein,

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer;

the at least one string driver region are two staggered regions at a center portion of the first CMOS wafer;

the at least one page buffer HV circuit region are two side portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two side portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two side portions of first CMOS wafer and the LV circuits of the page buffers in the two side portions of the second CMOS wafer.

11 . The 3D memory device according to claim 8 , wherein,

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer;

the at least one string driver region are two side portions of the first CMOS wafer;

the at least one page buffer HV circuit region are two center portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region is one center portion of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two center portions of first CMOS wafer and the LV circuits of the page buffers in the one center portion of the second CMOS wafer.

12 . The 3D memory device according to claim 8 , wherein,

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer;

the at least one string driver region are two side portions of the first CMOS wafer;

the at least one page buffer HV circuit region are two center portions of the first CMOS wafer for forming the HV circuits of the page buffers; and

the at least one page buffer region are two center portions of the second CMOS wafer for forming the LV circuits of the page buffers,

wherein the at least one page buffer region includes two through silicon connects (TSC) regions to connect the HV circuits of the page buffers in the two center portions of first CMOS wafer and the LV circuits of the page buffers in the two center portions of the second CMOS wafer.

13 . The 3D memory device according to claim 8 , wherein:

the at least one cell region are two side portions of the array wafer, and the at least one stair structure region is a single center portion of the array wafer; and

the second CMOS wafer further includes a controller in memory (CIM) structure formed in at least one CIM region of the third substrate to provide control functions for the 3D memory device,

wherein the at least one CIM region are two side portions of the second CMOS wafer.

14 . The 3D memory device according to claim 8 , wherein:

the at least one cell region is a single center portion of the array wafer, and the at least one stair structure region are two side portions of the array wafer; and

the second CMOS wafer further includes a controller in memory (CIM) structure formed in at least one CIM region of the third substrate to provide control functions for the 3D memory device,

wherein the at least one CIM region is a lower center portion of the second CMOS wafer.

15 . A memory system, comprising:

a 3D memory device, including an array wafer, a first complementary metal-oxide-semiconductor (CMOS) wafer, and a second CMOS wafer stacked together, the array wafer including a first substrate having at least one cell region and at least one stair structure region, a plurality of memory cells formed in the at least one cell region, and a stair structure formed in the at least one stair structure region; the first CMOS wafer including a second substrate having at least one string driver region corresponding to the at least one stair structure region and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region, HV circuits of a string driver formed in the at least one string driver region, and HV circuits of page buffers formed in the at least one page buffer HV circuit region; and the second CMOS wafer including a third substrate having at least one page buffer region corresponding to the at least one cell region, and low-voltage (LV) circuits of the page buffers formed in the at least one page buffer region, wherein the 3D memory device further comprises: an isolating layer formed over the first substrate; at least one through substrate contact penetrating the first substrate; and

one or more array pads in contact with the at least one through substrate contact, wherein the third substrate is combined with the first CMOS wafer; the LV circuits of the page buffer are formed on the third substrate and in the at least one page buffer region; the first CMOS wafer and the second CMOS wafer form a bonded first CMOS wafer and second CMOS wafer; and the array wafer is bonded to the bonded first CMOS wafer and second CMOS wafer at a bonding interface;

a memory controller coupled to the 3D memory device for controlling the 3D memory device; and

an external interface for communicating with a host for storing information in the 3D memory device.

16 . The memory system according to claim 15 , wherein the external interface includes one of universal serial bus (USB), secure digital (SD), compact flash (CF), solid state drive (SSD), and embedded multi-media-card (eMMC).