Integrated circuit device and method
An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.
1. An integrated circuit (IC) device comprising:
first through third active areas extending in a first direction; and
a first gate structure extending in a second direction perpendicular to the first direction and overlying each of the first through third active areas,
wherein
each of the first through third active areas comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint of the corresponding active area,
the first active area is positioned between the second and third active areas and comprises the endpoint positioned under the first gate structure along a third direction perpendicular to each of the first and second directions, and
each of the second and third active areas comprises the endpoint positioned away from the first gate structure in a fourth direction opposite to the first direction.
2. The IC device of claim 1 , wherein the first active area is positioned closer to one of the second or third active areas than to the other of the second or third active areas.
3. The IC device of claim 1 , wherein each of the first through third active areas comprises a plurality of fin structures.
4. The IC device of claim 1 , further comprising:
a conductive layer segment extending parallel to the first gate structure and overlying and electrically connected to one or more of the first through third active areas.
5. The IC device of claim 1 , further comprising:
a fourth active area extending in the first direction between the first active area and one of the second or third active areas,
wherein the fourth active area comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint positioned under the first gate structure along the third direction.
6. The IC device of claim 5 , wherein the fourth active area is positioned closer to the first active area than to each of the second and third active areas.
7. The IC device of claim 1 , further comprising:
a fourth active area extending in the first direction adjacent to one of the second or third active areas whereby the one of the second or third active areas is positioned between the first and fourth active areas,
wherein the fourth active area comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint positioned under the first gate structure along the third direction.
8. The IC device of claim 7 , wherein the first through fourth active areas have a uniform spacing.
9. The IC device of claim 1 , further comprising:
a second gate structure parallel to the first gate structure and overlying the second portion of each of the second and third active areas.
10. The IC device of claim 1 , further comprising:
a second gate structure parallel to the first gate structure and overlying the first portion of each of the first through third active areas.
11. An integrated circuit (IC) device comprising:
first through third active areas extending in a first direction; and
first and second gate structures extending in a second direction perpendicular to the first direction and overlying each of the first through third active areas, and positioned according to a gate pitch along the first direction,
wherein
each of the first through third active areas comprises:
a first portion adjacent to the first gate structure in the first direction and comprising a first endpoint of the corresponding active area; and
a second portion adjacent to the first portion and comprising a second endpoint of the corresponding active area,
the first active area is positioned between the second and third active areas and comprises:
the second endpoint positioned under the first gate structure along a third direction perpendicular to each of the first and second directions; and
the first endpoint separated from the second endpoint by a multiple of two or three times the gate pitch, and
each of the second and third active areas comprises the second endpoint positioned away from the first gate structure in a fourth direction opposite to the first direction.
12. The IC device of claim 11 , wherein the first active area is positioned closer to one of the second or third active areas than to the other of the second or third active areas.
13. The IC device of claim 11 , wherein each of the first through third active areas comprises a plurality of fin structures.
14. The IC device of claim 11 , further comprising:
a conductive layer segment extending parallel to the first and second gate structures and overlying and electrically connected to one or more of the first through third active areas.
15. The IC device of claim 11 , further comprising:
a fourth active area extending in the first direction between the first active area and one of the second or third active areas,
wherein the fourth active area comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint positioned under the first gate structure along the third direction.
16. The IC device of claim 11 , further comprising:
a fourth active area extending in the first direction adjacent to one of the second or third active areas whereby the one of the second or third active areas is positioned between the first and fourth active areas,
wherein the fourth active area comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint positioned under the first gate structure along the third direction.
17. A method of manufacturing an integrated circuit (IC) device, the method comprising:
forming first through third active areas extending in a first direction; and
fabricating a first gate structure extending in a second direction perpendicular to the first direction and overlying each of the first through third active areas,
wherein each of the first through third active areas comprises:
a first portion adjacent to the first gate structure in the first direction; and
a second portion adjacent to the first portion and comprising an endpoint of the corresponding active area,
the first active area is positioned between the second and third active areas and comprises the endpoint positioned under the first gate structure along a third direction perpendicular to each of the first and second directions, and
each of the second and third active areas comprises the endpoint positioned away from the gate structure in a fourth direction opposite to the first direction.
18. The method of claim 17 , wherein the forming the first through third active areas comprises forming the first active area closer to one of the second or third active areas than to the other of the second or third active areas.
19. The method of claim 17 , wherein the forming each of the first through third active areas comprises forming a plurality of fin structures.
20. The method of claim 17 , further comprising:
forming a conductive layer segment overlying and electrically connected to one or more of the first through third active areas.