Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same
A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
1. A semiconductor device, comprising:
a first logic cell that includes a first conductive line that is electrically connected to a first source and drain region;
a second logic cell that includes a second conductive line that is electrically connected to a second source and drain region and a third conductive line that is electrically connected to a third source and drain region, the second conductive line being adjacent to the first conductive line in a first direction; and
a dummy cell that includes a dummy line that is connected to a fourth source and drain region, the dummy line being adjacent to the third conductive line in the first direction,
wherein a first distance between the first conductive line and the second conductive line is shorter than a second distance between the third conductive line and the dummy line.
2. The semiconductor device of claim 1 , wherein the first conductive line and the second conductive line are formed by a patterning process using different photomasks.
3. The semiconductor device of claim 1 , further comprising:
a first power line and a second power line in the first direction.
4. The semiconductor device of claim 3 , wherein a ground voltage is provided to one of the first power line and the second power line.
5. The semiconductor device of claim 1 , wherein the dummy cell is one of a filler, a filling capacitor, and a spare cell.
6. The semiconductor device of claim 1 , further comprising:
a first active region that includes a first plurality of active lines extended in the first direction on a substrate;
a gate line crossing the first plurality of active lines in a second direction perpendicular to the first direction; and
a source area and a drain area on each active line located at opposite sides of the gate line.
7. The semiconductor device of claim 6 , further comprising:
a second active region that includes a second plurality of active lines extended in the first direction on the substrate.
8. The semiconductor device of claim 7 , wherein the first active region is a NMOS region and the second active region is a PMOS region.
9. The semiconductor device of claim 1 , further comprising:
a third logic cell that includes a fourth conductive line,
wherein the dummy line is a first dummy line,
wherein the dummy cell includes a second dummy line,
wherein the second dummy line is adjacent to the fourth conductive line in the first direction, and
wherein the first distance is shorter than a third distance between the second dummy line and the fourth conductive line.
10. The semiconductor device of claim 9 , wherein the second dummy line and the fourth conductive line are formed by a patterning process using a same photomask.
11. The semiconductor device of claim 1 , wherein the first conductive line and the second conductive line are provided at a first boundary between the first logic cell and the second logic cell, and
wherein the third conductive line and the dummy line are provided at a second boundary between the second logic cell and the dummy cell.
12. The semiconductor device of claim 1 , wherein the first distance and the second distance are set based on a resolution of a photolithography process for forming the first to third conductive lines and the dummy line.
13. A semiconductor device, comprising:
an active region that includes a plurality of active lines extended in a first direction on a substrate;
a first logic cell provided on an active line from among the plurality of active lines, the first logic cell including a first conductive line that is electrically connected to a first source and drain region;
a second logic cell provided on the active line, the second logic cell including a second conductive line that is electrically connected to a second source and drain region and a third conductive line that is electrically connected to a third source and drain region, and the second conductive line being adjacent to the first conductive line in the first direction; and
a dummy cell provided on the active line, the dummy cell including a dummy line that is connected to a fourth source and drain region, and the dummy line being adjacent to the third conductive line in the first direction,
wherein a first distance between the first conductive line and the second conductive line is shorter than a second distance between the third conductive line and the dummy line.
14. The semiconductor device of claim 13 , wherein the first conductive line and the second conductive line are formed by a patterning process using different photomasks.
15. The semiconductor device of claim 13 , wherein the first conductive line and the second conductive line are provided at a first boundary between the first logic cell and the second logic cell, and
wherein the third conductive line and the dummy line are provided at a second boundary between the second logic cell and the dummy cell.
16. The semiconductor device of claim 13 , further comprising:
a first power line and a second power line in the first direction,
wherein the first power line receive a power voltage and the second power line receive a ground voltage.
17. The semiconductor device of claim 13 , further comprising:
a gate line crossing the plurality of active lines in a second direction perpendicular to the first direction; and
a source area and a drain area on each active line located at opposite sides of the gate line.
18. A semiconductor device, comprising:
a first plurality of conductive lines for a first logic cell, a second logic cell, and a dummy cell; and
a second plurality of conductive lines for the first logic cell, the second logic cell, and the dummy cell,
wherein a first conductive line that is electrically connected to a first source and drain region, from among the first plurality of conductive lines, of the first logic cell is adjacent to a second conductive line that is electrically connected to a second source and drain region, from among the second plurality of conductive lines, of the second logic cell in a first direction,
wherein a third conductive line that is electrically connected to a third source and drain region, from among the second plurality of conductive lines, of the second logic cell is adjacent to a dummy line that is connected to a fourth source and drain region, from among the first plurality of conductive lines, of the dummy cell in the first direction, and
wherein a first distance between the first conductive line and the second conductive line is shorter than a second distance between the third conductive line and the dummy line.
19. The semiconductor device of claim 18 , wherein the first plurality of conductive lines and the second plurality of conductive lines are formed by a patterning process using different photomasks.
20. The semiconductor device of claim 18 , further comprising:
a first power line and a second power line in the first direction,
wherein the first power line receive a power voltage and the second power line receive a ground voltage.
21. The semiconductor device of claim 18 , further comprising:
a gate line crossing a plurality of active lines in a second direction perpendicular to the first direction; and
a source area and a drain area on each active line located at opposite sides of the gate line.