Integrated circuit packages and methods of forming the same
Embodiments include a method for forming an integrated circuit package. A first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. A first metallization pattern is formed extending along and through the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. The second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. After the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. The wafer and the first dielectric layer are sawed in the scribe line region.
1 . A method comprising:
depositing a first dielectric layer over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer;
forming a first metallization pattern extending along and through the first dielectric layer;
depositing a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region;
removing the second dielectric layer from the scribe line region, the second dielectric layer remaining in the package region;
after removing the second dielectric layer from the scribe line region, forming a second metallization pattern extending along and through the second dielectric layer; and
sawing the wafer and the first dielectric layer in the scribe line region.
2 . The method of claim 1 , wherein removing the second dielectric layer from the scribe line region comprises:
patterning the second dielectric layer to form openings and to remove the second dielectric layer from the scribe line region, the second metallization pattern being formed in the openings of the second dielectric layer.
3 . The method of claim 2 , wherein the second dielectric layer is formed of a photosensitive material, and patterning the second dielectric layer comprises exposing the photosensitive material to light.
4 . The method of claim 1 , wherein sawing the wafer and the first dielectric layer comprises:
forming a notch in the scribe line region of the wafer with a pre-sawing step; and
forming an opening in the scribe line region of the wafer with a main sawing step.
5 . The method of claim 1 , further comprising:
depositing a third dielectric layer over the second metallization pattern and the second dielectric layer, the third dielectric layer overlapping the package region and the scribe line region; and
removing the third dielectric layer from the scribe line region and from a sidewall of the second dielectric layer.
6 . The method of claim 1 , further comprising:
depositing a third dielectric layer over the second metallization pattern and the second dielectric layer, the third dielectric layer overlapping the package region and the scribe line region; and
removing the third dielectric layer from the scribe line region, the third dielectric layer remaining on a sidewall of the second dielectric layer.
7 . A method comprising:
forming a redistribution structure over an interposer, the interposer comprising through-substrate vias, the redistribution structure comprising:
a first dielectric layer;
a first metallization pattern extending along and through the first dielectric layer, the first metallization pattern comprising redistribution lines and a seal ring, the redistribution lines contacting the through-substrate vias, the seal ring extending around the redistribution lines in a top-down view, the seal ring being electrically isolated from the redistribution lines; and
a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer covering the seal ring and a first portion of the first dielectric layer, a second portion of the first dielectric layer being uncovered by the second dielectric layer; and
singulating the redistribution structure and the interposer by sawing the interposer and the second portion of the first dielectric layer.
8 . The method of claim 7 , further comprising:
attaching an integrated circuit device to a front side of the interposer, the redistribution structure being formed over a back side of the interposer; and
forming an encapsulant around the integrated circuit device, the encapsulant being singulated by the sawing.
9 . The method of claim 7 , further comprising:
connecting a package substrate to the redistribution structure; and
forming an underfill between the package substrate and the redistribution structure, the underfill covering the second portion of the first dielectric layer.
10 . The method of claim 9 , wherein sawing the interposer comprises sawing a notch in the interposer such that a sidewall of the interposer has a first portion and a second portion, the first portion of the sidewall forming an obtuse angle with the second portion of the sidewall, the first portion of the sidewall extending between the second portion of the sidewall and a back side of the interposer, the underfill contacting the first portion and the second portion of the sidewall.
11 . The method of claim 7 , wherein sawing the interposer and the second portion of the first dielectric layer comprises sawing through the first dielectric layer without sawing through the second dielectric layer.
12 . The method of claim 7 , wherein the seal ring contacts a surface of the interposer and does not contact any of the through-substrate vias.
13 . The method of claim 7 , wherein after the singulating, the seal ring is disposed between the redistribution lines and a sidewall of the first dielectric layer.
14 . The method of claim 7 , wherein the redistribution structure further comprises a second metallization pattern extending along and through the second dielectric layer, the second metallization pattern contacting the redistribution lines through the second dielectric layer, the seal ring remaining covered by the second dielectric layer and not contacted by the second metallization pattern.
15 . A method comprising:
attaching a first integrated circuit device and a second integrated circuit device to a front side of a wafer, wherein the wafer has a first package region, a second package region, and a scribe line region between the first package region and the second package region, wherein the first integrated circuit device is attached in the first package region, and the second integrated circuit device is attached in the second package region;
forming a redistribution structure by:
depositing a first dielectric layer on a back side of the wafer, the first dielectric layer overlapping the first package region, the second package region, and the scribe line region;
forming a first metallization pattern extending along and through the first dielectric layer;
depositing a second dielectric layer on the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the first package region, the second package region, and the scribe line region;
removing the second dielectric layer from the scribe line region while the second dielectric layer remains in the first package region and the second package region; and
after removing the second dielectric layer from the scribe line region, forming a second metallization pattern extending along and through the second dielectric layer; and
sawing the wafer and the redistribution structure in the scribe line region.
16 . The method of claim 15 , wherein the first dielectric layer remains in the scribe line region, and sawing the redistribution structure in the scribe line region comprises sawing through the first dielectric layer without sawing through the second dielectric layer.
17 . The method of claim 15 , wherein after the sawing, the first dielectric layer has a first width between sidewalls of the first dielectric layer in a cross-sectional view and the second dielectric layer has a second width between sidewalls of the second dielectric layer in the cross-sectional view, the second width being less than the first width.
18 . The method of claim 15 , wherein the first metallization pattern comprises redistribution lines and a seal ring, the seal ring extending around the redistribution lines in a top-down view, the seal ring being electrically isolated from the redistribution lines, wherein the second dielectric layer covers a top surface of the seal ring, and the second metallization pattern contacts the redistribution lines without contacting the seal ring.
19 . The method of claim 18 , wherein the seal ring contacts the back side of the wafer without contacting through-substrate vias of the wafer.
20 . The method of claim 15 , wherein removing the second dielectric layer from the scribe line region comprises patterning the second dielectric layer to form openings in the second dielectric layer and to remove the second dielectric layer from the scribe line region, and the second metallization pattern is formed in the openings of the second dielectric layer.