Semiconductor structure including lines of different height

1 . A method for manufacturing a semiconductor structure, comprising:

forming a first layer on a base structure, the first layer being made of a first electrically conductive material, and having a first region and a second region displaced from the first region, each of the first region and the second region including a conductive line;

patterning the first layer such that the conductive line at the first region is selectively recessed to have a recessed portion which has a first height and a non-recessed portion which has a second height that is greater than the first height and that is the same as a height of the conductive line at the second region;

forming a patterned dielectric layer over the patterned first layer such that the non-recessed portion is exposed from the patterned dielectric layer; and

forming a second layer over the patterned dielectric layer so as to permit the second layer to be connected to the non-recessed portion, the second layer being made of a second electrically conductive material,

wherein patterning the first layer includes:

forming a patterned masking unit which includes

forming a patterned first mask to cover the conductive line at the second region and to expose the first region, and

forming a patterned second mask to cover the non-recessed portion of the conductive line at the first region, the patterned second mask being made of a material different from a material of the patterned first mask; and

patterning the first layer through the patterned masking unit such that a portion of the conductive line at the first region, which is uncovered by the patterned masking unit, is recessed to form the recessed portion.

2 . The method according to claim 1 , wherein forming the patterned second mask includes:

forming a second mask layer over the patterned first mask and the first layer;

forming a protection mask layer over the second mask layer, the protection mask layer being made of a material different from a material of the second mask layer;

patterning the protection mask layer to form a cover mask that corresponds in position to the non-recessed portion of the conductive line at the first region; and

patterning the second mask layer through the cover mask, such that the patterned second mask covers the non-recessed portion of the conductive line at the first region.

3 . The method according to claim 1 , wherein the patterned second mask includes a section covering the non-recessed portion, a width of the section being greater than a width of the non-recessed portion.

4 . The method according to claim 1 , further comprising, forming an etch stop layer over the first layer,

prior to patterning the first layer, the etch stop layer being patterned to expose a portion of the conductive line at the first region,

in patterning the first layer, the portion of the conductive line at the first region being recessed to form the recessed portion, and

in forming the patterned dielectric layer, the patterned dielectric layer being formed over the patterned etch stop layer and the patterned first layer.

5 . A method for manufacturing a semiconductor structure, comprising:

forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines;

forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion;

forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion; and

forming a patterned etch stop layer on the patterned first layer, the patterned etch stop layer having a first portion which is formed around the first via, and a second portion which is disposed on the second lines,

wherein the upper surface of the connection portion is connected to both the first via and the first portion of the patterned etch stop layer.

6 . The method according to claim 5 , further comprising

prior to forming the first via and the second via, forming a patterned dielectric layer over the patterned first layer.

7 . The method according to claim 6 , wherein the first via and the second via are simultaneously formed in the patterned dielectric layer, and are made of a second electrically conductive material.

8 . The method according to claim 6 , further comprising,

forming a plurality of dielectric units such that two adjacent ones of the first lines and the second lines are spaced apart from each other by a corresponding one of the dielectric units.

9 . The method according to claim 8 , wherein each of the dielectric units has an upper surface at a level which is the same as a level of an upper surface of each of the second lines.

10 . The method according to claim 8 ,

wherein prior to forming the patterned dielectric layer, the patterned etch stop layer is formed, and

wherein after forming the patterned dielectric layer, the first lines are connected to the patterned dielectric layer.

11 . The method according to claim 8 , wherein each of the dielectric units includes an air gap therein.

12 . A method for manufacturing a semiconductor structure, comprising:

forming a first layer on a base structure, the first layer being made of a first electrically conductive material, and having a first region and a second region displaced from the first region, the first region including first conductive lines that extend lengthwise in a first direction, and that are spaced apart from each other in a second direction different from the first direction, the first conductive lines each having a bottom segment and an upper segment connected to each other along a third direction different from the first direction and the second direction, the second region including second conductive lines that extend lengthwise in the first direction, and that are spaced apart from each other in the second direction, and

forming a patterned first mask over the second conductive lines, the first region being uncovered by the patterned first mask;

forming a patterned second mask that covers a first part of the upper segment of a first predetermined one of the first conductive lines; and

performing a patterning process to pattern the first layer through the patterned first mask and the patterned second mask, such that a second part of the upper segment of the first predetermined one of the first conductive lines and the upper segment of a second predetermined one of the first conductive lines are removed, and such that the first part of the upper segment of the first predetermined one of the first conductive lines remains unpatterned, and such that the second conductive lines remain unpatterned.

13 . The method according to claim 12 , further comprising forming a second layer that is made of a second electrically conductive material, the second layer being connected to the first part of the upper segment of the first predetermined one of the first conductive lines.

14 . The method according to claim 12 , wherein the patterned second mask is formed after forming the patterned first mask.

15 . The method according to claim 12 , wherein:

before the patterning process, a height of the first conductive lines at the first region is same as a height of the second conductive lines at the second region measured in the third direction; and

after the patterning process, a height of the second predetermined one of the first conductive lines is smaller than a height of the second conductive lines measured in the third direction.

16 . The method according to claim 12 , wherein the patterned second mask and the patterned first mask are formed at the same time.

17 . The method according to claim 12 , wherein forming the patterned first mask includes:

sequentially depositing a mask layer and a photoresist layer over the first layer;

forming the photoresist layer into a patterned photoresist; and

patterning the mask layer through the patterned photoresist into the patterned first mask.

18 . The method according to claim 12 , further comprising forming a first via which is connected to an upper surface and a side surface of the first part of the upper segment of the first predetermined one of the first conductive lines.

19 . The method according to claim 5 , wherein a height of the connection portion is greater than 30 Å.

20 . The method according to claim 5 , wherein the connection portion and the part of the one of the first lines are integrally formed.