Pulse width control apparatus and method
View Patent ↗Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.
1. A system comprising:
a logic device configured to perform a logic operation to two of signals generated by an oscillator circuit, wherein the logic operation generates a pulse width modulation (PWM) signal having a duty cycle corresponding to the two signals and the logic device comprises:
first and second logic circuits configured to receive the two signals; and
a third logic circuit configured to output the PWM signal.
2. The system of claim 1 , wherein the logic device comprises a plurality of enhancement mode high electron mobility transistors (E-HEMTs) and a plurality of depletion mode high electron mobility transistors (D-HEMTs).
3. The system of claim 1 , wherein:
the first logic circuit is configured to receive a first signal of the two signals, the first logic circuit comprising a first E-HEMT coupled in series to a first D-HEMT;
the second logic circuit is configured to receive a second signal of the two signals, the second logic circuit comprising a second E-HEMT coupled in series to a second D-HEMT;
the logic device further comprises a fourth logic circuit coupled to the first logic circuit and the second logic circuit, the fourth logic circuit comprising a third E-HEMT and a fourth E-HEMT coupled together in series with a third D-HEMT; and
the third logic circuit is coupled to the fourth logic circuit, the third logic circuit comprising a fifth E-HEMT and a fourth D-HEMT.
4. The system of claim 3 , wherein the logic device further comprises a fifth logic circuit coupled between the third logic circuit and the fourth logic circuit, the fifth logic circuit comprising a sixth E-HEMT and a fifth D-HEMT.
5. The system of claim 2 , wherein the plurality of E-HEMTs and the plurality of D-HEMTs are n-type transistors.
6. The system of claim 1 , wherein the logic operation comprises at least one of a NOT gate, a NAND gate, or a NOR gate.
7. The system of claim 1 , further comprising a signal generator configured to delay an input signal to generate the signals, and the signal generator comprises the oscillator circuit.
8. The system of claim 1 , wherein the logic device comprises Gallium Nitride (GaN) components.
9. A device comprising:
a plurality of logic circuits comprising a plurality of high electron mobility transistors (HEMTs), the plurality of logic circuits configured to generate a pulse width modulation (PWM) signal based on signals generated by an oscillator circuit and to the plurality of logic circuits, wherein the plurality of logic circuits comprise:
first and second logic circuits configured to receive the signals; and
a third logic circuit configured to output the PWM signal.
10. The device of claim 9 , wherein the signals to the plurality of logic circuits comprise at least two signals generated by a signal generator and the PWM signal has a duty cycle signal that is based on duty cycles of the at least two signals.
11. The device of claim 9 , wherein:
the first logic circuit is configured to receive a first signal of the signals, the first logic circuit comprising a first E-HEMT (enhancement-HEMT) of the plurality of E-HEMTs coupled in series to a first D-HEMT (depletion-HEMT) of the plurality of D-HEMTs;
the second logic circuit is configured to receive a second signal of the signals, the second logic circuit comprising a second E-HEMT of the plurality of E-HEMTs coupled in series to a second D-HEMT of the plurality of D-HEMTs;
the plurality of logic circuits further comprise a fourth logic circuit coupled to the first logic circuit and the second logic circuit, the fourth logic circuit comprising a third E-HEMT and a fourth E-HEMT of the plurality of E-HEMTs coupled together in series with a third D-HEMT of the plurality of D-HEMTs; and
the third logic circuit is coupled to the fourth logic circuit, the third logic circuit comprising a fifth E-HEMT of the plurality of E-HEMTs and a fourth D-HEMT of the plurality of D-HEMTs.
12. The device of claim 11 , wherein the plurality of logic circuits further comprises a fifth logic circuit coupled between the third logic circuit and the fourth logic circuit, the fifth logic circuit comprising a sixth E-HEMT of the plurality of E-HEMTs and a fifth D-HEMT of the plurality of D-HEMTs.
13. The device of claim 9 , wherein the plurality of E-HEMTs and the plurality of D-HEMTs are n-type transistors.
14. The device of claim 9 , wherein the plurality of logic circuits comprises at least one of a NOT gate, a NAND gate, or a NOR gate.
15. The device of claim 10 , wherein the signal generator comprises the oscillator circuit.
16. The device of claim 9 , wherein the plurality of logic circuits comprise Gallium Nitride (GaN) components.
17. A method, comprising:
generating a pulse width modulation (PWM) signal with variable duty cycle modulation by performing a logic operation to two signals generated by an oscillator circuit, wherein the PWM signal is generated by:
receiving, by a first logic circuit and a second logic circuit, the two signals; and
generating, by a third logic circuit, the PWM signal.
18. The method of claim 17 , wherein the PWM signal is generated by:
generating, by the first logic circuit and a second logic circuit, clocking voltages configured to drive a fourth logic circuit;
performing, by the fourth logic circuit, a first logic operation to generate a first voltage output; and
generating, by the third logic circuit, the PWM signal by performing a second logic operation on the first voltage output.
19. The method of claim 18 , wherein:
the first logic circuit comprises a first E-HEMT coupled in series to a first D-HEMT;
the second logic circuit comprises a second E-HEMT coupled in series to a second D-HEMT;
the fourth logic circuit is coupled to the first logic circuit and the second logic circuit and comprises a third E-HEMT and a fourth E-HEMT coupled together in series with a third D-HEMT; and
the third logic circuit is coupled to the fourth logic circuit and comprises a fifth E-HEMT and a fourth D-HEMT.
20. The method of claim 18 , wherein the PWM signal is further generated by performing, by a fifth logic circuit coupled between the third logic circuit and the fourth logic circuit, a third logic operation.