Granted Patent B2

US 12,641,773 · App. 18/369,957 · Granted May 26, 2026

Inventor: Jhen-Yu Tsai (Kaohsiung City, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H10B12/34H10B12/053H10B12/315

Abstract

Claims (36)

1 . A semiconductor device, comprising:

a substrate having a trench; and

a gate structure in the trench, wherein the gate structure comprising:

a lower gate electrode;

an upper gate electrode disposed over the lower gate electrode;

a silicide layer contacting the upper gate electrode; and

a lower dielectric layer disposed between the lower gate electrode and the substrate;

wherein the lower gate electrode and the upper gate electrode are configured to receive different voltages, and the gate structure is disposed in an active region of the substrate;

wherein the silicide layer contacts the lower dielectric layer.

2 . The semiconductor device of claim 1 , further comprising:

a metal layer disposed between the lower gate electrode and the upper gate electrode.

3 . The semiconductor device of claim 2 , wherein the silicide layer is formed along an interface between the metal layer and the upper gate electrode.

4 . The semiconductor device of claim 2 , wherein the upper gate electrode is separated from the lower gate electrode by the metal layer and the silicide layer.

5 . The semiconductor device of claim 2 , wherein the upper gate electrode is separated from the lower dielectric layer by the metal layer and the silicide layer.

6 . The semiconductor device of claim 1 , further comprising:

a metal layer disposed between the lower dielectric layer and the upper gate electrode.

7 . The semiconductor device of claim 1 , further comprising:

a barrier layer disposed between the lower gate electrode and the substrate.

8 . The semiconductor device of claim 7 , wherein the barrier layer contacts the lower dielectric layer.

9 . The semiconductor device of claim 1 , further comprising:

an upper dielectric layer disposed between the upper gate electrode and the lower dielectric layer.

10 . The semiconductor device of claim 9 , wherein the upper gate electrode is separated from the lower gate electrode by the upper dielectric layer, the metal layer, and the silicide layer.

11 . The semiconductor device of claim 9 , wherein the silicide layer contacts the upper dielectric layer.

12 . A semiconductor device, comprising:

a substrate having a trench; and

a gate structure in the trench, wherein the gate structure comprising:

a lower gate electrode;

an upper gate electrode disposed over the lower gate electrode;

a metal layer disposed between the lower gate electrode and the upper gate electrode;

a lower dielectric layer disposed between the lower gate electrode and the substrate; and

a barrier layer disposed between the lower gate electrode and the substrate; and

an upper dielectric layer disposed between the upper gate electrode and the lower dielectric layer;

wherein the metal layer contacts the upper dielectric layer.

13 . The semiconductor device of claim 12 , wherein the upper gate electrode is surrounded by the metal layer.

14 . The semiconductor device of claim 12 , wherein the metal layer is disposed between the lower dielectric layer and the upper gate electrode.

15 . The semiconductor device of claim 12 , wherein the metal layer contacts the barrier layer.

Assignments (1)

Continuity (2)

References Cited (14)