Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices
A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.
1. A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:
a III-nitride substrate having a first conductivity type;
a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches;
a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;
a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;
a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;
a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer;
a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;
a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric;
and
a source metal layer coupled to an upper portion of the fourth III-nitride layer.
2. The vertical MOSFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
3. The vertical MOSFET device of claim 1 wherein a depth of the first plurality of first trenches extend an entire thickness of the first III-nitride layer.
4. The vertical MOSFET device of claim 1 wherein sidewalls of the first plurality of first trenches are parallel to a III-nitride m-plane.
5. The vertical MOSFET device of claim 1 wherein sidewalls of the second plurality of second trenches are parallel to a III-nitride m-plane.
6. The vertical MOSFET device of claim 1 wherein the second III-nitride structure comprises an epitaxially regrown layer.
7. The vertical MOSFET device of claim 1 wherein the gate dielectric is conformal to a sidewall and bottom wall of each of the second plurality of second trenches.
8. The vertical MOSFET device of claim 1 wherein the gate dielectric comprises multiple layers of individual dielectrics.
9. The vertical MOSFET device of claim 8 wherein each layer of the multiple layers of individual dielectrics comprises a unique dielectric.
10. The vertical MOSFET device of claim 1 wherein the gate metal layer comprises a refractory metal.