Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
View Patent ↗Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
1 . A memory system, comprising:
a plurality of memory portions; and
circuitry configured, in response to receiving a first command and a second command within a first duration, to:
perform a refresh operation at a first memory portion of the plurality of memory portions; and
perform a mode register read operation of a different kind than the refresh operation at the first memory portion.
2 . The memory system of claim 1 , wherein the circuitry is further configured to:
receive the first command during a first clock cycle; and
receive the second command during a second clock cycle that is a next consecutive clock cycle after the first clock cycle, wherein the first duration comprises the first clock cycle and the second clock cycle.
3 . The memory system of claim 2 , wherein the circuitry is further configured to:
receive the second command during the second clock cycle and a third clock cycle that is a next consecutive clock cycle after the second clock cycle, the first duration comprising the first clock cycle, the second clock cycle, and the third clock cycle.
4 . The memory system of claim 2 , wherein the first command and the second command are each received via a command/address bus.
5 . The memory system of claim 1 , wherein, to perform the mode register read operation, the circuitry is configured to:
output, during a second duration, data from a mode register of the memory system.
6 . The memory system of claim 5 , wherein the circuitry is further configured to:
receive, via a second chip select terminal, signaling comprising an indication for a second memory portion of the plurality of memory portions to provide on-die termination during at least a portion of the second duration.
7 . The memory system of claim 5 , wherein the data comprises information corresponding to a temperature of the first memory portion.
8 . The memory system of claim 5 , wherein the data comprises information corresponding to a refresh rate of the first memory portion.
9 . The memory system of claim 1 , wherein the circuitry is further configured to:
receive, via a first chip select terminal, signaling comprising an indication to perform the first command and the second command at the first memory portion.
10 . The memory system of claim 1 , wherein the first command comprises a refresh command and the second command comprises a mode register read command.
11 . A memory device, comprising:
a controller configured to cause the memory device to:
receive a refresh command;
receive a mode register read command; and
output, after receiving the refresh command and the mode register read command, data from a mode register of the memory device.
12 . The memory device of claim 11 , wherein the refresh command is received during a first clock cycle and the mode register read command is received during a second clock cycle that is a next consecutive clock cycle after the first clock cycle.
13 . The memory device of claim 12 , wherein the mode register read command is received during the second clock cycle and a third clock cycle that is a next consecutive clock cycle after the second clock cycle.
14 . The memory device of claim 11 , wherein the refresh command and the mode register read command are each received via a command/address bus.
15 . The memory device of claim 11 , wherein the data comprises information corresponding to a temperature of the memory device.
16 . The memory device of claim 11 , wherein the data comprises information corresponding to a refresh rate of the memory device.
17 . A method by a memory system, comprising:
receiving, during a first duration, a first command and a second command;
performing, in response to receiving the first command and the second command, a refresh operation at a first memory portion of a plurality of memory portions of the memory system; and
performing, in response to receiving the first command and the second command, a mode register read operation of a different kind than the refresh operation at the first memory portion.
18 . The method of claim 17 , further comprising:
receiving the first command during a first clock cycle; and
receiving the second command during a second clock cycle that is a next consecutive clock cycle after the first clock cycle, wherein the first duration comprises the first clock cycle and the second clock cycle.