Memory sensing with global counter
A circuit is provided. The circuit includes an array of memory cells including a plurality of bit lines and a plurality of word lines, sensing circuits configured to sense a difference between first and second currents on respective bit lines in selected bit lines and to produce outputs for the selected bit lines as a function of the difference, and a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal. Each sensing circuit, of the sensing circuits, can produce an output in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.
1 . A circuit, comprising:
an array of memory cells including a plurality of bit lines and a plurality of word lines;
sensing circuits configured to sense a difference between first and second currents on respective bit lines in selected bit lines and to produce outputs for the selected bit lines as a function of the difference; and
a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal,
wherein each sensing circuit, of the sensing circuits, produces an output, of the outputs, in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.
2 . The circuit of claim 1 ,
wherein the global counter is configured to continuously increment or decrement the count value over time, and
wherein, for a particular time, a same particular count value is provided to each of the sensing circuits.
3 . The circuit of claim 1 , wherein each sensing circuit, of the sensing circuits, includes a local detector circuit configured to:
receive a detected voltage (V c ) generated in dependence on the difference;
receive a reference voltage (V ref ); and
generate a trigger signal in dependence on the detected voltage (V c ) and the reference voltage (V ref ).
4 . The circuit of claim 3 ,
wherein each sensing circuit, of the sensing circuits, includes a storage configured to store a particular count value provided by the global counter, and
wherein the storing of the particular count value is performed in dependence on the trigger signal.
5 . The circuit of claim 4 , wherein the storage includes latches that store the particular count value provided by the global counter.
6 . The circuit of claim 4 , wherein the storage includes flip-flops that store the particular count value provided by the global counter.
7 . The circuit of claim 4 , wherein the local detector circuit includes a comparator configured to (i) compare the detected voltage (V c ) and the reference voltage (V ref ) and (ii) generate the trigger signal as a result of the detected voltage (V c ) reaching, exceeding or falling below the reference voltage (V ref ).
8 . The circuit of claim 7 , wherein the trigger signal generated by the comparator is edge triggered as the result of the detected voltage (V c ) reaching, exceeding or falling below the reference voltage (V ref ).
9 . The circuit of claim 7 , wherein the trigger signal generated by the comparator is level triggered as the result of the detected voltage (V c ) reaching or exceeding the reference voltage (V ref ).
10 . The circuit of claim 3 , wherein the local detector circuit includes a differential amplifier configured to generate the trigger signal in dependence on the detected voltage (V c ) and the reference voltage (V ref ).
11 . The circuit of claim 3 , wherein the local detector circuit includes an inverter configured to generate the trigger signal in dependence on the detected voltage (V c ) and the reference voltage (V ref ).
12 . The circuit of claim 3 , wherein the reference voltage (V ref ) is received by each sensing circuit, of the sensing circuits, from a global fixed reference voltage source, such that each sensing circuit receives the same reference voltage (V ref ).
13 . The circuit of claim 3 , wherein the reference voltage (V ref ) is received by each sensing circuit, of the sensing circuits, from a global adjustable reference voltage source, such that each sensing circuit receives the same reference voltage (V ref ).
14 . The circuit of claim 3 , wherein each sensing circuit, of the sensing circuits, operates according to the same global counter and the local detector circuit, as opposed to implementing a local analog-to-digital converter.
15 . The circuit of claim 1 , wherein each sensing circuit, of the sensing circuits, does not include a local analog-to-digital converter.
16 . The circuit of claim 1 , wherein the count value provided by the global counter is a binary value of at least two bits.
17 . The circuit of claim 1 , wherein the global counter is one of a regular counter and a non-regular counter.
18 . The circuit of claim 1 , wherein each sensing circuit, of the sensing circuits, includes:
a current manipulator circuit configured to sense a difference between a first sensed current (I 0 ) and a second sensed current (I 1 ) and to output a current (I cell ); and
a capacitor configured to receive the current (I cell ), to store a charge in dependence on the received current (I cell ) and to provide a detected voltage (V c ), resulting from the stored charge, to a detector circuit that triggers storing of the count value received from the global counter.
19 . A method for sensing currents on bits lines of an array of memory cells including a plurality of bit lines and a plurality of word lines and providing digital outputs, the method comprising:
sensing a difference, using sensing circuits, between first and second currents on respective bit lines in selected bit lines;
continuously receiving, by the sensing circuits, a count value provided from a global counter in dependence on a clock signal; and
producing, by the sensing circuits, the digital outputs for the selected bit lines as a function of the difference and the count value,
wherein a digital output, of the digital outputs, is produced by each sensing circuit, of the sensing circuits, in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.
20 . A circuit, comprising:
sensing circuits configured to sense a difference between first and second currents on respective bit lines, of an array of memory cells, in selected bit lines and to produce outputs for the selected bit lines as a function of the difference, and
wherein each sensing circuit, of the sensing circuits, produces an output, of the outputs, in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, the count value being stored in dependence on a value of the difference between the first and second currents.