Control signal generator for sense amplifier and memory device including the control signal generator
Provided is a control signal generator for a sense amplifier, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.
1. A control signal generator for a sense amplifier, the control signal generator comprising:
a replica circuit comprising replica transistors corresponding to at least some transistors among a plurality of transistors comprised in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and
an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.
2. The control signal generator of claim 1 , wherein
the sense amplifier is configured to receive a reference signal and a data input signal that varies according to data stored in a memory cell, and
the replica circuit is further configured to commonly receive the reference signal.
3. The control signal generator of claim 1 , wherein the replica circuit comprises a replica transistor that corresponds to an amplification enable transistor of the sense amplifier which receives the second control signal, and is configured to receive a signal equal to the second control signal that is inactivated.
4. The control signal generator of claim 1 , wherein the replica circuit comprises a replica transistor that corresponds to an equalization transistor of the sense amplifier which equalizes a differential output signal in response to the first control signal that is activated, and is configured to receive a signal equal to the activated first control signal.
5. The control signal generator of claim 1 , wherein the replica circuit comprises replica transistors that correspond to reset transistors of the sense amplifier which reset a differential output signal in response to the first control signal that is activated, and are configured to receive the first control signal.
6. The control signal generator of claim 1 , wherein the replica circuit is further configured to receive a third control signal for enabling input transistors of the sense amplifier which receive the at least one input signal.
7. The control signal generator of claim 1 , wherein
the replica circuit comprises replica transistors corresponding to amplification transistors of the sense amplifier, the amplification transistors being for the amplifying operation, and
the amplifying circuit comprises transistors having respective same sizes as the amplification transistors.
8. The control signal generator of claim 1 , wherein the amplifying circuit comprises an inverter configured to output the second control signal by inverting the output signal from the replica circuit.
9. A control signal generator for a sense amplifier, the control signal generator comprising:
a replica circuit comprising replica transistors corresponding to transistors comprised in the sense amplifier, and configured to generate an output signal for emulating an output from the sense amplifier, in response to a first control signal for enabling a sensing operation by the sense amplifier; and
an amplifying circuit configured to output, by amplifying the output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.
10. The control signal generator of claim 9 , wherein
the sense amplifier is configured to receive a reference signal and a data input signal that varies according to data stored in a memory cell, and
the replica circuit is further configured to commonly receive the reference signal.
11. The control signal generator of claim 9 , wherein the amplifying circuit is further configured to amplify the output signal from the replica circuit when the output signal from the replica circuit corresponds to the output from the sense amplifier, wherein the output provides a maximum gain by amplification transistors of the sense amplifier and the amplification transistors are for the amplifying operation.
12. A memory device comprising:
a memory cell;
a sense amplifier configured to sense and amplify a data input signal that varies according to data stored in the memory cell;
a controller configured to generate a first control signal for enabling a sensing operation by the sense amplifier; and
a control signal generator configured to generate, from the first control signal, a second control signal for enabling an amplifying operation by the sense amplifier,
wherein the control signal generator comprises a replica circuit corresponding to the sense amplifier, and an amplifying circuit configured to generate the second control signal by amplifying an output signal from the replica circuit.
13. The memory device of claim 12 , wherein
the sense amplifier is further configured to receive a reference signal and the data input signal, and
the replica circuit is configured to commonly receive the reference signal.
14. The memory device of claim 13 , wherein
the memory cell is configured to store data according to a resistance value of a variable resistance element comprised in the memory cell and provide, to the sense amplifier, a read voltage as the data input signal, and
the memory device further comprises a reference circuit that comprises a reference resistor and is configured to generate a reference voltage as the reference signal.
15. The memory device of claim 12 , wherein
the sense amplifier comprises an amplification enable transistor configured to receive the second control signal, and
the replica circuit comprises a replica transistor corresponding to the amplification enable transistor, the replica transistor being configured to receive a signal equal to the second control signal that is inactivated.
16. The memory device of claim 12 , wherein
the sense amplifier comprises an equalization transistor configured to equalize a differential output signal, in response to the first control signal that is activated, and
the replica circuit comprises a replica transistor corresponding to the equalization transistor, the replica transistor being configured to receive a signal equal to the activated first control signal.
17. The memory device of claim 12 , wherein
the sense amplifier comprises reset transistors configured to reset a differential output signal, in response to the first control signal that is activated, and
the replica circuit comprises replica transistors corresponding to the reset transistors, the replica transistors being configured to receive the first control signal.
18. The memory device of claim 12 , wherein
the sense amplifier comprises an input transistor configured to receive the data input signal,
the controller is further configured to generate a third control signal for enabling the input transistor, and
the replica circuit is configured to receive the third control signal.
19. The memory device of claim 18 , wherein the controller is further configured to activate the second control signal after activating the third control signal.
20. The memory device of claim 12 , wherein
the sense amplifier comprises amplification transistors for the amplifying operation,
the replica circuit comprises replica transistors corresponding to the amplification transistors, and
the amplifying circuit comprises transistors having respective same sizes as the amplification transistors.