IP Library Granted Patent US 12,125,894
Granted Patent B2
US 12,125,894 · App. 18/383,926 · Granted Oct 22, 2024

Bipolar transistor

Inventors: Alexis Gauthier (Meylan, FR); Pascal Chevalier (Chapareillan, FR)
Assignees: STMicroelectronics (Crolles 2) SAS; STMicroelectronics France
H01L29/66272H01L29/0649H01L29/0821H01L29/732H01L21/26513
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Quick Facts
Patent No.
US 12,125,894
App. No.
18/383,926
Granted
Oct 22, 2024
Kind
B2
Abstract

A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

Claims (43)

1. A method of manufacturing a bipolar transistor, comprising:

forming a ring cavity in a semiconductor substrate, said ring cavity surrounding a first region of the semiconductor substrate;

depositing a doped polysilicon layer on walls and a bottom of the ring cavity;

filling a remaining part of the ring cavity with an insulating material to form an insulating ring trench over the doped polysilicon layer;

diffusing dopants of the doped polysilicon layer into the semiconductor substrate to form a diffused region in the semiconductor substrate; and

epitaxially growing an epitaxial region in contact with the first region of the substrate;

wherein the first region, the epitaxial region, the doped polysilicon layer and diffused region form a collector of the bipolar transistor.

2. The method of claim 1 , further comprising implanting dopant into the semiconductor substrate to form said first region of the semiconductor substrate, and wherein the ring cavity has a depth greater than a depth of the first region.

3. The method of claim 1 , wherein the doped polysilicon layer is substantially homogeneously doped and wherein the diffused region is gradually doped with a relatively higher doping level closer to the doped polysilicon layer.

4. The method of claim 1 , further comprising:

forming a base region of the bipolar transistor over and in contact with the epitaxial region; and

forming an emitter region of the bipolar transistor over the base region.

5. The method of claim 1 , further comprising:

forming a stack of a first insulating layer, a conductive layer and a second insulating layer over an upper surface of the first region of the semiconductor substrate; and

forming a cavity extending through the stack to reach the upper surface of the first region of the semiconductor substrate;

wherein epitaxially growing comprises epitaxially growing the epitaxial region within the cavity from the upper surface of the first region of the substrate.

6. The method of claim 5 , further comprising laterally etching away a portion of the conductive layer in the stack surrounding the cavity, wherein the epitaxial region formed by epitaxially growing produces an air pocket where said portion of the conductive layer in the stack was laterally etched away, said air pocket insulating the epitaxial region from the conductive layer.

7. The method of claim 6 , wherein the conductive layer is a polysilicon layer.

8. The method of claim 5 , further comprising:

forming a base region of the bipolar transistor over and in contact with the epitaxial region; and

forming an emitter region of the bipolar transistor over the base region.

9. The method of claim 8 , further comprising forming an extrinsic portion of the base region from the polysilicon layer.

10. A bipolar transistor, comprising:

a semiconductor substrate;

a ring trench in the semiconductor substrate, said ring trench surrounding a first region of the semiconductor substrate;

wherein the ring trench comprises: a diffused region in the semiconductor substrate; a doped polysilicon layer over the diffused region; and an insulating fill over the doped polysilicon layer;

an epitaxial region in contact with the first region of the substrate;

wherein the first region, the epitaxial region, the doped polysilicon layer and diffused region form a collector of the bipolar transistor.

11. The bipolar transistor of claim 10 , wherein the ring trench has a depth greater than a depth of the first region.

12. The bipolar transistor of claim 10 , wherein the doped polysilicon layer is substantially homogeneously doped and wherein the diffused region is gradually doped with a relatively higher doping level closer to the doped polysilicon layer.

13. The bipolar transistor of claim 10 , further comprising:

a base region of the bipolar transistor over and in contact with the epitaxial region; and

an emitter region of the bipolar transistor over the base region.

14. The bipolar transistor of claim 10 , further comprising:

a stack of a first insulating layer, a conductive layer and a second insulating layer over an upper surface of the first region of the semiconductor substrate; and

a cavity extending through the stack to reach the upper surface of the first region of the semiconductor substrate;

wherein the epitaxial region is located within the cavity.

15. The bipolar transistor of claim 14 , wherein a portion of the conductive layer in the stack surrounding the cavity is removed, and wherein the epitaxial region produces an air pocket where said removed portion of the conductive layer in the stack is located, said air pocket insulating the epitaxial region from the conductive layer.

16. The bipolar transistor of claim 15 , wherein the conductive layer is a polysilicon layer.

17. The bipolar transistor of claim 14 , further comprising:

a base region of the bipolar transistor over and in contact with the epitaxial region; and

an emitter region of the bipolar transistor over the base region.

18. The bipolar transistor of claim 17 , wherein the polysilicon layer forms an extrinsic portion of the base region.

Assignments (2)
CONFIRMATORY ASSIGNMENT Recorded May 23, 2024
From: CHEVALIER, PASCAL
To: STMICROELECTRONICS FRANCE (FKA STMICROELECTRONICS SA)
Reel/Frame 067527/0105 →
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
Priority Claims (1)
FR 1859284 · Oct 8, 2018 · national
Continuity (3)
Continuation 17685780 · Mar 3, 2022
Division 16591312 · Oct 2, 2019
Related Publication 20240063290A1 · Feb 22, 2024