Memory device, memory control device and operating method of memory device for checking command and address (CA) signal with predetermined pattern of command
A memory device includes: a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers further is configured to sample a corresponding first CA signal among the plurality of first CA signals; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers.
1. A memory device comprising:
a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers is further configured to sample a corresponding first CA signal among the plurality of first CA signals; and
a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers,
wherein the plurality of CA samplers are further configured to:
receive a first row-no-operation (RNOP) command and a first column-no-operation (CNOP) command as a plurality of second CA signals before receiving the command comprising the predetermined pattern; and
receive a second RNOP command and a second CNOP command as a plurality of third CA signals after receiving the command comprising the predetermined pattern.
2. The memory device of claim 1 , wherein the first RNOP command corresponds to one or more second CA signals among the plurality of second CA signals,
wherein the first RNOP command comprises high levels over a plurality of first consecutive clock cycles,
wherein the first CNOP command corresponds to one or more other second CA signals among the plurality of second CA signals,
wherein the first CNOP command comprises the high levels over the plurality of first consecutive clock cycles,
wherein the second RNOP command corresponds to one or more third CA signals among the plurality of third CA signals,
wherein the second RNOP command comprises the high levels over a plurality of second consecutive clock cycles,
wherein the second CNOP command corresponds to one or more other third CA signals among the plurality of third CA signals, and
wherein the second CNOP command comprises the high levels over the plurality of second consecutive clock cycles.
3. The memory device of claim 2 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals has a low level at a beginning clock cycle of the command having the predetermined pattern.
4. The memory device of claim 2 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have a low level at a last clock cycle of the command having the predetermined pattern.
5. The memory device of claim 1 , wherein the predetermined pattern comprises a pattern for testing the CA bus.
6. The memory device of claim 1 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals toggle from a high level to a low level or from the low level to the high level.
7. The memory device of claim 1 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have high levels over a plurality of consecutive clock cycles, and subsequently, change to low levels.
8. The memory device of claim 1 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have low levels over a plurality of consecutive clock cycles, and subsequently, change to high levels.
9. The memory device of claim 1 , wherein the command decoder is further configured to enter a CA training mode based on the parity error occurring in the plurality of first CA signals.
10. A memory control device comprising:
a clock generating circuit configured to provide a clock to a memory device via a clock bus; and
a command and address (CA) generating circuit configured to provide, as a plurality of first CA signals, a command comprising a predetermined pattern to the memory device via a CA bus, based on an exist of a sleep mode of the memory device,
wherein the CA generating circuit is further configured to:
provide, as a plurality of second CA signals, a first row-no-operation (RNOP) command and a first column-no-operation (CNOP) command to the memory device before providing the command having the predetermined pattern; and
provide, as a plurality of third CA signals, a second RNOP command and a second CNOP command to the memory device after providing the command having the predetermined pattern.
11. The memory control device of claim 10 , wherein the first RNOP command corresponds to one or more second CA signals among the plurality of second CA signals,
wherein the first RNOP command has high levels over a plurality of first consecutive clock cycles,
wherein the first CNOP command corresponds to one or more other second CA signals among the plurality of second CA signals,
wherein the first CNOP command comprises the high levels over the plurality of first consecutive clock cycles,
wherein the second RNOP command corresponds to one or more third CA signals among the plurality of third CA signals,
wherein the second RNOP command has the high levels over a plurality of second consecutive clock cycles,
wherein the second CNOP command corresponds to one or more other third CA signals among the plurality of third CA signals, and
wherein the second CNOP command comprises the high levels over the plurality of second consecutive clock cycles.
12. The memory control device of claim 11 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals has a low level at a beginning clock cycle of the command having the predetermined pattern.
13. The memory control device of claim 11 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have a low level at a last clock cycle of the command having the predetermined pattern.
14. The memory control device of claim 10 , wherein the predetermined pattern comprises a pattern for testing the CA bus.
15. The memory control device of claim 10 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals toggle from a high level to a low level or from the low level to the high level.
16. The memory control device of claim 10 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have high levels over a plurality of consecutive clock cycles and then change to low levels.
17. The memory control device of claim 10 , wherein the predetermined pattern comprises a pattern in which one or more first CA signals among the plurality of first CA signals have low levels over a plurality of consecutive clock cycles and then change to high levels.
18. A method of operating a memory device, comprising:
exiting from a sleep mode of the memory device;
receiving a first row-no-operation (RNOP) command and a first column-no-operation (CNOP) command via a command and address (CA) bus over a plurality of first clock cycles, wherein the first RNOP command and the first CNOP command comprise a predetermined type;
receiving a command having a predetermined pattern via the CA bus over a plurality of second clock cycles after the plurality of first clock cycles; and
receiving a second RNOP command and a second CNOP command having the predetermined type via the CA bus over a plurality of third clock cycles after the plurality of second clock cycles.