Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method
A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.
1. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
the first trigger signal line is between the plurality of power lines and the pixel array region;
the plurality of power lines comprise a third power line, at least one of the plurality of cascaded first shift registers of the first scan driving circuit further comprises a fourth constituting transistor connected to the third power line, and an orthographic projection of the fourth constituting transistor on the base substrate is on a side, away from an orthographic projection of the first signal line group on the base substrate, of an orthographic projection of the third power line on the base substrate;
the plurality of power lines comprise a first power line configured to provide a first power voltage, and an orthographic projection of the first power line on the base substrate partially overlaps with an orthographic projection of the first scan driving circuit on the base substrate,
wherein the second signal line group is on a side of the first scan driving circuit adjacent to the pixel array region, and
the first signal line group is on a side of the first scan driving circuit opposite to the side of the first scan driving circuit where the second signal line group is located,
wherein the plurality of power lines comprise a fourth power line,
an orthographic projection of the fourth power line on the base substrate partially overlaps with an orthographic portion of the first scan driving circuit on the base substrate,
wherein at least one of the plurality of cascaded first shift registers of the first scan driving circuit further comprises a fifth constituting transistor connected to the fourth power line, and
an orthographic projection of the fifth constituting transistor on the base substrate is between the orthographic projection of the fourth power line on the base substrate and an orthographic projection of the second signal line group on the base substrate.
2. The display substrate according to claim 1 , wherein at least one of the plurality of cascaded first shift registers of the first scan driving circuit comprises a first constituting transistor which is connected to the first power line,
an orthographic projection of the first constituting transistor on the base substrate is between the orthographic projection of the first signal line group on the base substrate and the orthographic projection of the first power line on the base substrate,
a gate of the first constituting transistor is connected to a second node, and a second electrode of the first constituting transistor is connected to the first power line to receive the first power voltage.
3. The display substrate according to claim 2 , wherein the first signal line group comprises a second clock signal line which is configured to provide a second clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
a gate electrode of the fifth constituting transistor is connected to a first node, a first electrode of the fifth constituting transistor is connected to the third power line to receive a second power voltage, and a second electrode of the fifth constituting transistor is connected to an output terminal of the first shift register.
4. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
the first trigger signal line is between the plurality of power lines and the pixel array region;
the plurality of power lines comprise a third power line, at least one of the plurality of cascaded first shift registers of the first scan driving circuit further comprises a fourth constituting transistor connected to the third power line, and an orthographic projection of the third power line on the base substrate is between an orthographic projection of the fourth constituting transistor on the base substrate and an orthographic projection of the first signal line group on the base substrate,
wherein the second signal line group is on a side of the first scan driving circuit adjacent to the pixel array region, and
the first signal line group is on a side of the first scan driving circuit opposite to the side of the first scan driving circuit where the second signal line group is located,
wherein the plurality of power lines comprise a fourth power line,
an orthographic projection of the fourth power line on the base substrate partially overlaps with an orthographic portion of the first scan driving circuit on the base substrate,
wherein at least one of the plurality of cascaded first shift registers of the first scan driving circuit further comprises a fifth constituting transistor connected to the fourth power line, and
an orthographic projection of the fifth constituting transistor on the base substrate is between the orthographic projection of the fourth power line on the base substrate and an orthographic projection of the second signal line group on the base substrate.
5. The display substrate according to claim 4 , wherein
an orthographic projection of the third power line on the base substrate is between the orthographic projection of the fourth power line on the base substrate and an orthographic projection of the first signal line group on the base substrate.
6. The display substrate according to claim 4 , wherein the third power line and the fourth power line are configured to provide a same second power voltage.
7. The display substrate according to claim 4 , wherein the first signal line group comprises a first clock signal line which is configured to provide a first clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit.
8. The display substrate according to claim 7 , wherein a gate electrode of the fourth constituting transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the fourth constituting transistor is connected to the third power line to receive a second power voltage, and a second electrode of the fourth constituting transistor is connected to a second node.
9. A display device, comprising the display substrate according to claim 8 .
10. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
the first trigger signal line is between the plurality of power lines and the pixel array region;
the first scan driving circuit comprises a first transistor, a second transistor, and a third transistor, and the first transistor, the second transistor, and the third transistor are respectively connected to the first signal line group,
an extending direction of a channel of the first transistor, an extending direction of a channel of the second transistor, and an extending direction of a channel of the third transistor are parallel to an extending direction of the first signal line group and an extending direction of the second signal line group;
the display substrate further comprises at least one first resistor, the first resistor is on a side, away from the first-stage first shift register, of the first scan driving circuit, the first trigger signal line is connected to the first-stage shift register of the first scan driving circuit through the first resistor;
the display substrate further comprises at least one first connection line and at least one second connection line, the first connection line connects one terminal of the first resistor with the first-stage shift register of the first scan driving circuit, and
the second connection line connects other terminal of the first resistor with the first trigger signal line;
the display substrate further comprises a first conductive connection portion, a second conductive connection portion, a first insulation layer, and a second insulation layer,
the first conductive connection portion and the second conductive connection portion are on a side, away from the base substrate, of both the first connection line and the second connection line, and are disposed in a same layer as the plurality of power lines, the first signal line group, and the second signal line,
the first insulation layer is between the first resistor and both of the first connection line and the second connection line in the direction perpendicular to the base substrate, and the second insulation layer is between both of the first connection line and second connection line, and, both of the first conductive connection portion and the second conductive connection portion in the direction perpendicular to the base substrate;
one terminal of the first conductive connection portion is connected to one terminal of the first connection line through a penetrating through the second insulation layer, and the other terminal of the first conductive connection portion is connected to one terminal of the first resistor through a hole penetrating through the first insulation layer and the second insulation layer,
other terminal of the first connection line is connected to the first-stage shift register of the first scan driving circuit;
one terminal of the second conductive connection portion is connected to one terminal of the second connection line through a hole penetrating through the second insulation layer, other terminal of the second conductive connection portion is connected to other terminal of the first resistor through a hole penetrating through the first insulation layer and the second insulation layer, and
other terminal of the second connection line is connected to the first trigger signal line through a hole penetrating through the second insulation layer.
11. The display substrate according to claim 10 , wherein
the first signal line group comprises a first clock signal line which is configured to provide a first clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
a gate electrode of the first transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the first transistor is connected to an input terminal of the first shift register, and a second electrode of the first transistor is connected to a first node.
12. The display substrate according to claim 10 , wherein
the first signal line group comprises a first clock signal line which is configured to provide a first clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
a gate electrode of the second transistor is connected to a first node, a first electrode of the second transistor is connected to the first clock signal line to receive the first clock signal, and a second electrode of the second transistor is connected to a second node.
13. The display substrate according to claim 10 , wherein
the first signal line group comprises a first clock signal line which is configured to provide a first clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
the plurality of power lines comprise a third power line configured to provide a second power voltage, a gate electrode of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the third power line to receive the second power voltage, and a second electrode of the third transistor is connected to a second node.
14. The display substrate according to claim 10 , wherein the first scan driving circuit further comprises a sixth transistor and a seventh transistor, the sixth transistor and the seventh transistor are respectively connected to the first signal line group, and an extending direction of a channel of the sixth transistor and an extending direction of a channel of the seventh transistor are parallel to the extending direction of the first signal line group and the extending direction of the second signal line group.
15. The display substrate according to claim 14 , wherein the first signal line group comprises a second clock signal line which is configured to provide a second clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
a gate electrode of the sixth transistor is connected to a second node, a first electrode of the sixth transistor is connected to the second clock signal line to receive the second clock signal, and a second electrode of the sixth transistor is connected to a third node.
16. The display substrate according to claim 14 , wherein the first signal line group comprises a second clock signal line which is configured to provide a second clock signal to the plurality of cascaded shift registers comprised in the first scan driving circuit,
a gate electrode of a seventh transistor is connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor is connected to a third node, and a second electrode of the seventh transistor is connected to the fourth node.