Transistor stack circuit
A transistor stack circuit including a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors, and a plurality of resistors is provided. The transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. A first terminal of each resistor is coupled to a common path. A second terminal of each resistor is coupled to a control terminal of a corresponding transistor among the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each resistor, and the transistors form a low-impedance path.
1 . A transistor stack circuit, comprising:
a first signal transmission port;
a second signal transmission port;
a plurality of transistors, connected in series to each other, and coupled between the first signal transmission port and the second signal transmission port;
a plurality of first resistors, wherein each of the first resistors has a first terminal and a second terminal, the first terminals are coupled to a common path, and each of the second terminals is coupled to a control terminal of a corresponding transistor among the transistors; and
an impedance unit, coupled between the common path and a reference voltage terminal, wherein
when an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each of the first resistors, and the transistors form a low-impedance path.
2 . The transistor stack circuit as claimed in claim 1 , wherein the impedance value of the impedance unit is less than 10 MΩ.
3 . The transistor stack circuit as claimed in claim 1 , wherein a number of the transistors is greater than 40, and the impedance value of the impedance unit is greater than 20 times of the resistance value of each of the first resistors.
4 . The transistor stack circuit as claimed in claim 1 , wherein a number of the transistors is greater than 10, and the impedance value of the impedance unit is greater than 5 times of the resistance value of each of the first resistors.
5 . The transistor stack circuit as claimed in claim 1 , wherein the impedance unit comprises:
a resistive element, having a first terminal and a second terminal respectively coupled to the common path and the reference voltage terminal.
6 . The transistor stack circuit as claimed in claim 1 , wherein the impedance unit comprises:
a capacitor; and
a resistive element, wherein the capacitor and the resistive element are connected in series or in parallel to each other between the common path and the reference voltage terminal,
wherein a product of a capacitance value of the capacitor and a resistance value of the resistive element is greater than a duration of the electrostatic discharge event.
7 . The transistor stack circuit as claimed in claim 1 , wherein the impedance unit comprises:
a resistive element; and
a first switch, wherein the resistive element and the first switch are connected in series between the common path and the reference voltage terminal.
8 . The transistor stack circuit as claimed in claim 7 , wherein
in a normal operation mode, the first switch is turned off; and
when the electrostatic discharge event occurs, the first switch is turned on.
9 . The transistor stack circuit as claimed in claim 7 , further comprising:
a second switch, wherein a first terminal of the second switch is coupled between the common path and the impedance unit, and a second terminal of the second switch is coupled to an internal circuit.
10 . The transistor stack circuit as claimed in claim 9 , wherein
in a normal operation mode, the first switch is turned off, and the second switch is turned on; and
when the electrostatic discharge event occurs, the first switch is turned on, and the second switch is turned off.
11 . The transistor stack circuit as claimed in claim 1 , further comprising:
an electrostatic discharge detection circuit, coupled to the first signal transmission port for detecting the electrostatic discharge event, wherein
when the electrostatic discharge event occurs, the impedance unit provides a current path between the common path and the reference voltage terminal, and
in a normal operation mode, the current path is cut off.
12 . The transistor stack circuit as claimed in claim 11 , wherein the electrostatic discharge detection circuit is coupled between the first signal transmission port, an internal circuit, and the reference voltage terminal, and the electrostatic discharge detection circuit comprises:
a detection resistor; and
a capacitor, wherein the detection resistor and the capacitor are connected in series between the first signal transmission port and the reference voltage terminal.
13 . The transistor stack circuit as claimed in claim 11 , wherein the impedance unit comprises:
a resistive element; and
a switch circuit, wherein the resistive element and the switch circuit are connected in series between the common path and the reference voltage terminal.
14 . The transistor stack circuit as claimed in claim 13 , wherein the switch circuit comprises:
a switch series, having a common control terminal coupled to an internal circuit, wherein the switch series is turned off in the normal operation mode, and the switch series is turned on when the electrostatic discharge event occurs; and
a diode, having a cathode coupled to the switch series.
15 . The transistor stack circuit as claimed in claim 1 , wherein the transistors comprise:
a first transistor;
a second transistor; and
a terminal transistor, wherein a first terminal of the first transistor is coupled to the first signal transmission port, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the terminal transistor is coupled to the second signal transmission port, and when the electrostatic discharge event occurs, the second transistor is turned on.
16 . The transistor stack circuit as claimed in claim 1 , wherein a voltage of each of the first terminals of the first resistors coupled to the common path is the same.
17 . The transistor stack circuit as claimed in claim 1 , further comprising:
a plurality of third resistors, wherein each of the third resistors is coupled between the first terminals of two corresponding first resistors that are adjacent to each other among the first resistors.
18 . The transistor stack circuit as claimed in claim 1 , wherein the transistor stack circuit is a radio frequency switch shunt path, the first signal transmission port is coupled to a radio frequency connection pad, and the second signal transmission port is coupled to the reference voltage terminal.
19 . The transistor stack circuit as claimed in claim 1 , wherein the transistor stack circuit is a radio frequency switch series path, the first signal transmission port is coupled to a radio frequency connection pad, and the second signal transmission port is coupled to a radio frequency switch shunt path.
20 . A transistor stack circuit, comprising:
a first signal transmission port;
a second signal transmission port;
a plurality of transistors, connected in series to each other, and coupled between the first signal transmission port and the second signal transmission port, wherein the transistors comprise a first transistor, a second transistor, and a terminal transistor, a first terminal of the first transistor is coupled to the first signal transmission port, a second terminal of the first transistor is coupled to a first terminal of the second transistor, and a second terminal of the terminal transistor is coupled to the second signal transmission port;
a plurality of first resistors, wherein each of the first resistors has a first terminal and a second terminal, wherein the first terminals are coupled to a common path, and each of the second terminals is coupled to a control terminal of a corresponding transistor among the transistors; and
an impedance unit, coupled between the common path and a reference voltage terminal, wherein
when an electrostatic discharge event occurs, a voltage difference between a control terminal of the second transistor and a second terminal of the second transistor is greater than a turn-on voltage of the second transistor.