Return address stack with branch mispredict recovery
Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.
1 . A processor-implemented method for predicting addresses comprising:
accessing a processor core, wherein the processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic, wherein the processor core is coupled to a memory system;
sending, to a branch execution unit, a write pointer, a read pointer, and a RAS count;
detecting one or more call instructions in an instruction stream, wherein the detecting generates a predicted return address for each of the one or more call instructions;
pushing, on the RAS, the predicted return address for each of the one or more call instructions, wherein the pushing is directed by the write pointer;
recognizing one or more return instructions in the instruction stream;
updating the write pointer and the read pointer for the RAS, wherein the updating is based on a misprediction signal from the branch execution unit and wherein the updating includes manipulating the RAS count;
popping, from the RAS, the predicted return address for each of the one or more return instructions wherein the popping is directed by the read pointer; and
rolling back, by the branch execution unit, the write pointer, the read pointer, and the RAS count to a previous value.
2 . The method of claim 1 wherein the sending is accomplished every cycle.
3 . The method of claim 2 wherein a pipeline flush is executed or a branch instruction is mispredicted, and wherein the branch instruction is not a call or a return instruction.
4 . The method of claim 3 further comprising returning, to the RAS, the write pointer, the read pointer, and the RAS count which were backed up.
5 . The method of claim 2 further comprising adjusting, by the branch execution unit, the write pointer, the read pointer, and the RAS count, wherein a call instruction from the one or more call instructions is mispredicted.
6 . The method of claim 5 further comprising returning, to the RAS, the write pointer, the read pointer, and the RAS count which were adjusted.
7 . The method of claim 2 further comprising adjusting the write pointer, the read pointer, and the RAS count, wherein a return instruction from the one or more return instructions is mispredicted.
8 . The method of claim 7 further comprising returning, to the RAS, the write pointer, the read pointer, and the RAS count which were adjusted.
9 . The method of claim 1 wherein the processor core executes one or more instructions out of order.
10 . The method of claim 9 wherein the pushing further comprises incrementing the RAS count as part of the manipulating.
11 . The method of claim 10 wherein the popping further comprises decrementing the RAS count as part of the manipulating.
12 . The method of claim 11 further comprising ignoring the one or more return instructions, wherein the RAS count is not zero.
13 . The method of claim 1 wherein the pushing further comprises updating, in the RAS, a next pointer field indexed by the write pointer with contents of the read pointer.
14 . The method of claim 13 further comprising updating the read pointer with contents of the write pointer.
15 . The method of claim 14 further comprising incrementing the write pointer.
16 . The method of claim 1 wherein the popping further comprises updating the read pointer with contents of a next pointer field indexed by the read pointer.
17 . The method of claim 1 wherein the predicted return address is the address of one of the one or more call instructions+4 bytes.
18 . The method of claim 1 further comprising initiating the RAS, wherein the initiating sets the write pointer and the read pointer to an initial value.
19 . The method of claim 1 wherein the RAS comprises eight entries.
20 . The method of claim 1 wherein the RAS comprises a Last-In-First-Out (LIFO) memory element.
21 . The method of claim 1 wherein the pushing includes storing data in the RAS at a location specified by the write pointer.
22 . The method of claim 1 wherein the popping includes reading data which was last stored in the RAS, wherein location of the data which was last stored is specified by the read pointer.
23 . A computer program product embodied in a non-transitory computer readable medium for predicting addresses, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:
accessing a processor core, wherein the processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic, wherein the processor core is coupled to a memory system;
sending, to a branch execution unit, a write pointer, a read pointer, and a RAS count;
detecting one or more call instructions in an instruction stream, wherein the detecting generates a predicted return address for each of the one or more call instructions;
pushing, on the RAS, the predicted return address for each of the one or more call instructions, wherein the pushing is directed by the write pointer;
recognizing one or more return instructions in the instruction stream;
updating the write pointer and the read pointer for the RAS, wherein the updating is based on a misprediction signal from the branch execution unit and wherein the updating includes manipulating the RAS count;
popping, from the RAS, the predicted return address for each of the one or more return instructions wherein the popping is directed by the read pointer; and
rolling back, by the branch execution unit, the write pointer, the read pointer, and the RAS count to a previous value.
24 . An apparatus for predicting addresses comprising:
a processor core coupled to a memory wherein the processor core and the memory are used to perform operations comprising:
accessing the processor core, wherein the processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic, wherein the processor core is coupled to a memory system;
sending, to a branch execution unit, a write pointer, a read pointer, and a RAS count;
detecting one or more call instructions in an instruction stream, wherein the detecting generates a predicted return address for each of the one or more call instructions;
pushing, on the RAS, the predicted return address for each of the one or more call instructions, wherein the pushing is directed by the write pointer;
recognizing one or more return instructions in the instruction stream;
updating the write pointer and the read pointer for the RAS, wherein the updating is based on a misprediction signal from the branch execution unit and wherein the updating includes manipulating the RAS count;
popping, from the RAS, the predicted return address for each of the one or more return instructions wherein the popping is directed by the read pointer; and
rolling back, by the branch execution unit, the write pointer, the read pointer, and the RAS count to a previous value.