Method to improve speed of executing return branch instructions in a processor
An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.
1. A method for executing call branch and return branch instructions in a processor, the method comprising:
setting a counter to an initial value in response to the processor decoding link register manipulating instructions other than call branch instructions;
incrementing the counter by a first constant in response to the processor decoding a call branch instruction;
pushing onto a link register stack an address of a next in program order instruction in response to the processor decoding the call branch instruction;
incrementing the counter by a second constant in response to the processor decoding a return branch instruction provided the counter has a value not equal to the initial value;
popping from the link register stack a target address for the return branch instruction in response to the processor decoding the return branch instruction provided the counter has a value not equal to the initial value, wherein when the value of the counter is not equal to the initial value, the target address popped from the link register stack is a correct target address for the return branch instruction; and
completing execution of and retiring the return branch instruction without checking the target address for correctness.
2. The method of claim 1 , wherein
the initial value is zero;
the first constant is equal to one; and
the second constant is equal to negative one.
3. An apparatus comprising:
a link register;
a link register stack;
a branch counter; and
a processor configured to:
set the branch counter to an initial value in response to decoding instructions other than call branch instructions that write to the link register;
increment the branch counter by a first constant in response to decoding a call branch instruction;
push onto the link register stack an address of a next in program order instruction in response to the processor decoding the call branch instruction;
increment the branch counter by a second constant in response to decoding a return branch instruction provided the branch counter has a value not equal to the initial value;
pop from the link register stack a target address for the return branch instruction in response to the processor decoding the return branch instruction provided the branch counter has a value not equal to the initial value, wherein when the value of the branch counter is not equal to the initial value, the target address popped from the link register stack is a correct target address for the return branch instruction; and
complete execution of and retire the return branch instruction without checking the target address for correctness.
4. The apparatus of claim 3 , wherein
the initial value is zero;
the first constant is equal to one; and
the second constant is equal to negative one.
5. The apparatus of claim 3 , wherein the apparatus is chosen from the set consisting of a cellular phone and a base station.