Electronic device for manufacturing of semiconductor device and operating method of electronic device
An operating method of a circuit design system which includes a processor and a memory includes reading, at the processor, a circuit layout of a flash memory device including a page buffer from the memory, initializing, at the processor, a value of a first parameter of at least one transistor of the page buffer and a value of a second parameter of at least one voltage applied to the page buffer, performing, at the processor, circuit simulation on the page buffer using the initialized first and second parameters, and calculating, at the processor, a reward based on a result of the circuit simulation. The processor is configured to perform, in response to the reward being not greater than a threshold value, a subsequent action. The subsequent action includes adjust the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage, and perform subsequent circuit simulation on the page buffer using the adjusted first and second parameters.
1 . An operating method of a circuit design system which includes a processor and a memory, the method comprising:
reading, at the processor, a circuit layout of a flash memory device including a page buffer from the memory;
initializing, at the processor, a value of a first parameter of at least one transistor of the page buffer and a value of a second parameter of at least one voltage applied to the page buffer;
performing, at the processor, circuit simulation on the page buffer using the initialized first and second parameters; and
calculating, at the processor, a reward based on a result of the circuit simulation,
wherein in response to the reward being not greater than a threshold value, the processor is configured to perform a subsequent action, and
wherein the subsequent action includes:
adjust the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage; and
perform subsequent circuit simulation on the page buffer using the adjusted first and second parameters.
2 . The method of claim 1 , further comprising:
storing a policy including probabilities of taking actions which are associated with the first and second parameters in the memory,
wherein the adjusting of the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage is performed based on the probabilities of the policy.
3 . The method of claim 2 ,
wherein, in response to the reward being greater than the threshold value, updating, at the processor, the probabilities of the policy.
4 . The method of claim 3 ,
wherein the updating of the probabilities of the policy is performed using the value of the first parameter and the value of the second parameter.
5 . The method of claim 1 , further comprising:
repeating the subsequent action until one of a reward obtained from the circuit simulation of the subsequent action being greater than the threshold value and the number of repeating the subsequent action reaching a maximum number is satisfied.
6 . The method of claim 1 ,
wherein the page buffer includes:
a latch connected to a sensing node; and
a first transistor connected between the sensing node and a bit line, and
wherein the at least one transistor includes the first transistor.
7 . The method of claim 1 ,
wherein the page buffer includes:
a latch connected to a sensing node; and
a first transistor connected between the sensing node and a bit line, and
wherein the at least one voltage includes a voltage applied to a gate of the first transistor.
8 . The method of claim 1 ,
wherein the page buffer includes:
a latch connected to a sensing node; and
a first transistor connected between the sensing node and a bit line,
wherein the latch includes a first inverter and a second inverter that are cross-coupled with each other, and
wherein the at least one transistor includes transistors of the first inverter and transistors of the second inverter.
9 . The method of claim 1 ,
wherein the flash memory device further includes;
a memory cell; and
a bit line connected to the memory cell,
wherein the page buffer includes:
a latch connected to a sensing node; and
a transistor connected between the sensing node and the bit line, and
wherein the performing of the circuit simulation includes:
detecting a trip voltage level of the sensing node, wherein a bit value of the latch is inverted at the trip voltage level;
measuring a first time point at which a voltage of the sensing node which is connected to the memory cell in an on-cell state is decreased from a precharge voltage level to the trip voltage level;
measuring a voltage difference between a voltage level of the sensing node which is connected to the memory cell in an off-cell state and the trip voltage level at the first time point; and
measuring an amount of power consumption of the page buffer.
10 . The method of claim 9 , further comprising:
receiving, at the processor, at least one of the first time point, the voltage difference, and the amount of the power consumption as reward parameters,
wherein the calculating of the reward includes:
calculating a weighted sum of the reward parameters.
11 . The method of claim 10 ,
wherein the first parameter is associated with a sum or an average of a first area of the at least one transistor, and
wherein the calculating of the reward further includes:
multiplying the weighted sum with a ratio of the sum or the average of the first area to a sum or an average of a target area of the at least one transistor.
12 . The method of claim 10 ,
wherein the calculating of the reward further includes:
multiplying the weighted sum with a constant value representing a process variation of a process which is to be applied to fabricate the page buffer.
13 . The method of claim 10 ,
wherein the calculating of the reward further includes:
multiplying the weighted sum with a word line factor, and
wherein the word line factor is determined based on the first and second parameters.
14 . The method of claim 1 ,
wherein in response to one of the reward obtained from the subsequent circuit simulation of the subsequent action being greater than the threshold value and the number of repeating the subsequent action reaching the maximum number being satisfied, performing, at the processor, a subsequent episode in which the circuit simulation of the page buffer is performed using the first and second parameters which are adjusted in a previous episode, and
wherein the repeating of the subsequent episode is performed in a predetermined number of episodes.
15 . An operating method of a circuit design system which includes a processor and a memory, the method comprising:
reading, at the processor, a circuit layout of a flash memory device including a page buffer from the memory; and
performing, at the processor, a plurality of episodes on the circuit layout based on a policy,
wherein each of the plurality of episodes includes:
performing, at the processor, circuit simulation on the circuit layout-circuit based on a value of a first parameter of at least one transistor of the page buffer and a value of a second parameter of at least one voltage applied to the page buffer;
calculating, at the processor, a reward based on reward parameters calculated based on a result of the circuit simulation; and
performing a subsequent action on the circuit layout-circuit until a reward of the subsequent action is greater than a threshold value, and
wherein the subsequent action includes:
adjusting the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage;
performing subsequent circuit simulation on the page buffer using the adjusted first and second parameters; and
calculating the reward based on a result of the subsequent circuit simulation.
16 . The method of claim 15 , further comprising:
storing a policy including probabilities of taking actions which are associated with the first and second parameters in the memory,
wherein each of the plurality of episodes further includes:
updating the probabilities of the policy based on adjustments of the first and second parameters, and a change in the reward of the subsequent action.
17 . The method of claim 16 ,
wherein the probabilities of the policy are associated with a direction of adjusting the first and second parameters.
18 . The method of claim 16 , further comprising:
updating, in response to a reward of a current action being greater than the threshold value, the probabilities of the policy in a direction that the reward of the subsequent action increases.
19 . The method of claim 15 ,
selecting, in response to the number of a plurality of episodes reaching a predetermined number, a parameter of the at least one transistor and a parameter of the at least one voltage, which correspond to a reward being the highest from among rewards calculated in the plurality of episodes.
20 . A circuit design system comprising:
a memory configured to store a circuit layout of a flash memory device including a page buffer; and
a processor configured to:
read the circuit layout from the memory, and
perform a plurality of episodes on the circuit layout based on a policy,
wherein the policy is updated in each episode of the plurality of episodes, and
wherein, in each of the plurality of episodes,
the processor is configured to:
perform circuit simulation on the page buffer based on a first parameter of at least one transistor of the page buffer and a second parameter of at least one voltage applied to the page buffer;
calculate a reward based on reward parameters calculated through the circuit simulation;
adjust values of the first and second parameters; and
repeat the circuit simulation, the adjustment of the first and second parameters, and the calculation of the reward, until the reward is greater than a threshold value.