Page buffer circuit and memory device including the same
A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.
1. A non-volatile memory device comprising:
a memory cell;
a bit line connected to the memory cell;
a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line;
a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter;
a third transistor connected among the first transistor, the second transistor, and a ground power; and
a control circuit for operating the first transistor and the second transistor at least once during a period in which the third transistor is turned on, wherein at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged comprises the period the third transistor is turned on.
2. The non-volatile memory device of claim 1 , wherein:
the third transistor is turned on for the initialize period, and
the initialize period includes a first period in which the first transistor is turned on and a second period in which the second transistor is turned on after the first period.
3. The non-volatile memory device of claim 1 , wherein:
the initialize period includes a first period in which the third transistor is turned on,
the precharge period includes a second period in which the third transistor is turn on,
the first period includes a period in which the first transistor is turned on, and
the second period includes a period in which the second transistor is turned on.
4. The non-volatile memory device of claim 1 , further comprising:
a second cross coupled inverter for sensing data stored in the memory cell through the sensing node; and
a fourth transistor connected between the third transistor and a first end of the second cross coupled inverter and transmitting a ground voltage to a first end of the second cross coupled inverter; and
a fifth transistor connected between the third transistor and a second end of the second cross coupled inverter and transmitting the ground voltage to a second end of the second cross coupled inverter.
5. The non-volatile memory device of claim 4 , wherein:
the third transistor is turned on in the initialize period, and
the initialize period includes a first period in which the first transistor and the fourth transistor are turned on and a second period in which the second transistor and the fifth transistor are turned on after the first period.
6. The non-volatile memory device of claim 5 , wherein:
the initialize period includes a first period in which the third transistor is turned on,
the precharge period includes a second period in which the third transistor is turned on,
the first period includes a period in which the first transistor and the fourth transistor are turned on, and
the second period includes a period in which the second transistor and the fourth transistor are turned on.
7. The non-volatile memory device of claim 5 , wherein:
the initialize period includes a first period in which the third transistor is turned on,
the precharge period includes a second period in which the third transistor is turned on,
the first period includes a third period in which the first transistor is turned on and a fourth period in which the second transistor is turned on after the third period, and
the second period includes a fifth period in which the fourth transistor is turned on and a sixth period in which the fifth transistor is turned on after the fifth period.
8. A non-volatile memory device comprising:
a memory cell;
a bit line connected to the memory cell;
a cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line as a latch value;
a first transistor for connecting a first end of the cross coupled inverter to ground when the sensing node is connected to ground according to the latch value;
a second transistor for connecting a second end of the cross coupled inverter to ground when a voltage at the sensing node is maintained according to the latch value;
a third transistor connected among the first transistor, the second transistor, and a ground power;
a fourth transistor having a first end connected to the sensing node; and
a fifth transistor connected between a second end of the fourth transistor and the ground power and controlled according to the latch value,
wherein the fourth transistor is turned on,
wherein the fifth transistor is turned on according to the latch value, so the voltage at the sensing node is discharged to ground,
wherein the third transistor and the first transistor are turned on, and
wherein the voltage at the first end of the cross coupled inverter is discharged to ground.
9. The non-volatile memory device of claim 8 , further comprising a sixth transistor connected between a first end of the second transistor and the ground power and controlled by the voltage at the sensing node.
10. The non-volatile memory device of claim 9 , wherein the fourth transistor is turned on, the fifth transistor is turned off according to a voltage at the first end of the cross coupled inverter to maintain the voltage at the sensing node, the third transistor and the first transistor are turned on to maintain the voltage at the first end of the cross coupled inverter as ground, the second transistor is turned on, and the sixth transistor is turned on according to the voltage at the sensing node to discharge the voltage at the second end of the cross coupled inverter to ground, so the voltage at the first end of the cross coupled inverter is inverted.
11. A method for driving a non-volatile memory device comprising:
connecting a sensing node, which is connected to a bit line of a memory cell, to ground and discharging the sensing node for an initialize period;
precharging the bit line for a precharge period;
sensing data stored in the memory cell by using a first cross coupled inverter connected to the sensing node;
turning on a third transistor connected between the ground and a first transistor and a second transistor connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to the respective ends of the first cross coupled inverter within at least one of the initialize period and the precharge period; and
respectively operating, at least once, the first transistor and the second transistor during the third transistor is turned on.
12. The method of claim 11 , wherein:
the respectively operating, at least once, of the first transistor and the second transistor includes:
initializing a set terminal of the first cross coupled inverter for a first period within the initialize period; and
initializing a reset terminal of the first cross coupled inverter for a second period after the first period within the initialize period.
13. The method of claim 11 , wherein:
the respectively operating, at least once, of the first transistor and the second transistor includes:
initializing a set terminal of the first cross coupled inverter for a first period within the initialize period; and
initializing a reset terminal of the first cross coupled inverter for a second period within the precharge period.
14. The method of claim 11 , further comprising:
sensing data stored in the memory cell by using a second cross coupled inverter connected to the sensing node; and
respectively operating, at least once, a fourth transistor and a fifth transistor connected to respective ends of the second cross coupled inverter and respectively transmitting a ground voltage to respective ends of the second cross coupled inverter within at least one of the initialize period and the precharge period.
15. The method of claim 14 , wherein:
the respectively operating, at least once, of the first transistor and the second transistor includes:
initializing a set terminal of the first cross coupled inverter for a first period within the initialize period; and
initializing a reset terminal of the first cross coupled inverter for a second period after the first period within the initialize period, and
the respectively operating, at least once, of the fourth transistor and the fifth transistor includes:
initializing a set terminal of the second cross coupled inverter for a third period within the initialize period; and
initializing a reset terminal of the second cross coupled inverter for a fourth period after the third period within the initialize period.
16. The method of claim 14 , wherein:
the respectively operating, at least once, of the first transistor and the second transistor includes:
initializing a set terminal of the first cross coupled inverter for a first period within the initialize period; and
initializing a reset terminal of the first cross coupled inverter for a second period within the precharge period, and
the respectively operating, at least once, of the fourth transistor and the fifth transistor includes:
initializing a set terminal of the second cross coupled inverter for a third period within the initialize period; and
initializing a reset terminal of the second cross coupled inverter for a fourth period within the precharge period.
17. The method of claim 14 , further comprising:
initializing a value latched to the first cross coupled inverter by:
initializing a set terminal of the first cross coupled inverter for a first period within the initialize period; and
initializing a reset terminal of the first cross coupled inverter for a second period after the first period within the initialize period, wherein:
respectively operating, at least once, of the fourth transistor and the fifth transistor includes:
initializing a set terminal of the second cross coupled inverter for a third period within the precharge period; and
initializing a reset terminal of the second cross coupled inverter for a fourth period within the precharge period.