Adaptive clock signal frequency scaling
Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
1. Adaptive frequency scaling circuitry having synchronizing dynamic and fixed clock signals, the circuitry comprising:
dynamic clock gating circuitry configured to modulate an input clock signal based on one or more performance values to produce a dynamic clock signal with an adjustable frequency;
fixed clock gating circuitry coupled to the dynamic clock gating circuitry and configured to output a fixed clock signal from the dynamic clock signal, wherein the fixed clock gating circuitry maintains the output of the fixed clock signal when the dynamic clock gating circuitry modulates the input clock signal for causing a frequency change to the adjustable frequency; and
packet processing circuitry including a shared packet buffer, wherein the one or more performance values includes a queue length of the shared packet buffer.
2. The circuitry of claim 1 , wherein the fixed clock gating circuitry is further configured to maintain the frequency of the fixed clock signal by gating the dynamic clock signal based on a fixed clock gating control value, thereby synchronizing the fixed clock signal with the dynamic clock signal during the frequency change.
3. The circuitry of claim 1 , wherein the dynamic clock gating circuitry is further configured to selectively gate the input clock signal based on a dynamic clock gating control value, the dynamic clock control value based on one or more performance indicators.
4. The circuitry of claim 3 , wherein the one or more performance indicators include one or more of: a link rate, a link activity status, one or more queue lengths in a buffer, a total interface rate from at least one link, a buffer link activity of a total interface rate, a minimum interface rate, a maximum interface rate, a link activity, or a buffer queue length.
5. The circuitry of claim 4 , further comprising a trigger circuitry configured for dynamic adjustment of clock frequencies, the trigger circuitry configured for:
determining a change to the one or more performance indicators; and
causing the scaling circuitry to output a new clock gating control value based the change to the one or more performance indicators.
6. The circuitry of claim 4 , further comprising a trigger circuitry configured for:
determining a number of cycles (n); and
causing, when the number of cycles (n) corresponds to a predetermined integer number, the scaling circuitry to output a new dynamic clock gating control value.
7. The circuitry of claim 1 , wherein the dynamic clock gating circuitry is configured for frequency change adjustments corresponding to +/−1% of an original clock frequency.
8. A circuitry for adaptive clock frequency scaling in a data processing system having a dynamic clock configured to output a dynamic clock signal and a fixed clock configured to output a fixed clock signal, the circuitry comprising:
an interface rate circuitry configured to determine rates of data transfer across one or more interfaces of the data processing system and determine clock gating control values based on the rates of data transfer;
a plurality of lookup tables configured to correlate one or more performance indicators to the clock gating control values; and
a selection circuitry configured to utilize the plurality of look up tables to determine the clock gating control values to be applied to dynamic and fixed clock gating circuitries, thereby synchronizing the fixed clock signal to the dynamic clock signal.
9. The circuitry of claim 8 , further comprising a scaling control circuitry, the scaling control circuitry comprising an interface rate analysis circuitry configured to:
determine the highest interface rate from active links between the data processing system and/or one or more external devices; and
determine a dynamic clock gating control value based on this highest interface rate.
10. The circuitry of claim 9 , wherein the scaling control circuitry includes a highest interface rate lookup table configured to correlate the highest interface rate to a corresponding dynamic clock gating control value, for selecting the control value based on the determined highest interface rate.
11. The circuitry of claim 9 , wherein the scaling control circuitry includes a total interface rate lookup table configured to correlate a total interface rate, based on a plurality of active links, to a dynamic clock gating control value, thereby allowing a frequency of the dynamic clock signal to be adjusted based on a cumulative data transfer rate of the system.
12. The circuitry of claim 11 , wherein the total interface rate is based on a plurality of active links of the data processing system and/or external devices.
13. The circuitry of claim 11 , wherein the scaling control circuitry includes a queue length lookup table configured to correlate a queue length value to dynamic clock gating control values, thereby facilitating an adjustment of the frequency of the dynamic clock signal based on a data processing load.
14. The circuitry of claim 13 , further comprising a packet processing circuitry having a shared packet buffer, wherein the queue length value corresponds to a number of packets in the shared packet buffer.
15. The circuitry of claim 9 , wherein the scaling control circuitry comprises a selection circuitry configured to determine a final dynamic clock gating control value based on a maximum value of performance metrics corresponding to the dynamic clock gating control.
16. The circuitry of claim 15 , wherein the maximum value of performance metrics are based on one or more of: the highest interface rate, total interface rate, and queue length lookup tables.
17. A method for synchronizing clocks in adaptive frequency scaling for a data processing system, the method comprising:
modulating, using a dynamic clock gating circuitry, an input clock signal to produce a dynamic clock signal with an adjustable frequency;
outputting a fixed clock signal from the dynamic clock signal using a fixed clock gating circuitry, wherein the fixed clock signal is constant when the adjustable frequency undergoes an adjustment
determining one or more performance indicators based on one or more of an interface rate or a queue length;
determining a clock gating control value based on the one or more performance indicators;
outputting the clock gating control value to cause the adjustment of the dynamic clock signal; and
outputting the fixed clock signal, the fixed clock signal being synchronized to the dynamic clock signal.
18. The method of claim 17 , wherein selecting clock gating control values based on analyzed performance indicators includes:
determining, utilizing a first lookup table, a highest interface rate;
determining, utilizing a second lookup table, a total interface rate;
determining, utilizing a third lookup table, a queue length value;
determining, based on the highest interface rate, the total interface rate, and the queue length value, a maximum clock gating control value; and
outputting a clock control signal based on the maximum clock gating control value.