Transistor assemblies with gate current shunting capability, and associated methods
A transistor assembly with gate current shunting capability includes first field effect transistor (FET), a first pull-up current source, a first pull-down current source, a first switching device, a control circuit, a capacitor, and a second FET. The first FET is an N-channel FET including a first gate, a first drain, and a first source. The first drain is electrically coupled to a first power supply. Each of the pull-up current source and the pull-down current source is electrically coupled to the first gate. The first switching device is electrically coupled in series with the first pull-down current source and is controlled by a first control signal. The control circuit is at least partially powered by a second power supply and generates the first control signal. The capacitor and the second FET collectively shunt current away from the first gate during a pre-power operating state of the transistor assembly.
1 . A transistor assembly with gate current shunting capability, comprising:
a first field effect transistor (FET) including a first gate, a first drain, and a first source, the first FET being an N-channel FET, and the first drain being electrically coupled to a first power supply;
a first pull-up current source electrically coupled to the first gate;
a first pull-down current source electrically coupled to the first gate;
a first switching device electrically coupled in series with the first pull-down current source, the first switching device being configured to be controlled by a first control signal;
a control circuit at least partially powered by a second power supply and configured to generate the first control signal to control an operating state of the first FET; and
a capacitor and a second FET collectively configured to shunt current away from the first gate during a pre-power operating state of the transistor assembly, the pre-power operating state of the transistor assembly being characterized at least partially by (a) the first power supply being active and (b) the second power supply being inactive.
2 . The transistor assembly of claim 1 , wherein the capacitor is electrically coupled to a gate of the second FET.
3 . The transistor assembly of claim 1 , wherein:
the second FET is an N-channel FET including a second gate, a second drain, and a second source;
the second drain is electrically coupled to the first gate; and
the capacitor is electrically coupled between the first power supply and the second gate.
4 . The transistor assembly of claim 3 , wherein the second source is electrically coupled to the first source.
5 . The transistor assembly of claim 3 , wherein the second source is electrically coupled to a reference node.
6 . The transistor assembly of claim 3 , further comprising a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.
7 . The transistor assembly of claim 6 , wherein the control circuit is further configured to assert the second control signal when the second power supply is active, and thereby cause the second switching device to operate in its on-state.
8 . The transistor assembly of claim 6 , further comprising a resistor, the second switching device and the resistor being electrically coupled in series between the second gate and a reference node.
9 . The transistor assembly of claim 1 , further comprising a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.
10 . The transistor assembly of claim 9 , wherein the control circuit is further configured to assert the second control signal and thereby cause the second switching device to operate in its on-state when the second power supply is active.
11 . A method for shunting current away from a gate of a first N-channel field effect transistor (FET) including a drain electrically coupled to a first power supply, the method comprising:
charging a gate-to-source capacitance of a second N-channel FET via a capacitor electrically coupled to a gate of the second N-channel FET;
shunting current away from the gate of the first N-channel FET via the second N-channel FET, a drain of the second N-channel FET being electrically coupled to the gate of the first N-channel FET; and
discharging the gate-to-source capacitance of the second N-channel FET in response to a second power supply becoming active.
12 . The method of claim 11 , wherein shunting current away from the gate of the first N-channel FET via the second N-channel FET comprises shunting current around a gate-to-source capacitance of the first N-channel FET.
13 . The method of claim 11 , wherein shunting current away from the gate of the first N-channel FET via the second N-channel FET comprises shunting current from the gate of the first N-channel FET to a reference node.
14 . The method of claim 11 , wherein the second power supply is configured to power a control circuit that is configured to control an operating state of the first N-channel FET.
15 . An electrical circuit configured to be electrically coupled to a load, comprising:
a first power supply;
a second power supply; and
a transistor assembly, including:
a first field effect transistor (FET) and a second FET, the first FET and the second FET being configured to be electrically coupled in series between the first power supply and the load, each of the first FET and the second FET being a respective N-channel FET,
a control circuit at least partially powered by the second power supply, the control circuit being configured to control a respective operating state of each of the first FET and the second FET, and
a capacitor and a third FET collectively configured to shunt current away from a gate of the first FET during a pre-power operating state of the transistor assembly characterized at least partially by (a) the first power supply being active and (b) the second power supply being inactive.
16 . The electrical circuit of claim 15 , wherein the load comprises a camera.
17 . The electrical circuit of claim 15 , wherein:
the third FET comprises a gate and a drain;
the capacitor is electrically coupled between the first power supply and the gate of the third FET; and
the drain of the third FET is electrically coupled to the gate of the first FET.
18 . The electrical circuit of claim 17 , wherein a source of the third FET is electrically coupled to one of (a) a source of the first FET and (b) a reference node.
19 . The electrical circuit of claim 17 , further comprising a switching device configured to discharge a gate-to-source capacitance of the third FET in response to a signal asserted after the second power supply is active.
20 . The electrical circuit of claim 16 , wherein the camera is a camera of an automobile.