CMOS data clearing circuit

1 . A CMOS data clearing circuit for clearing CMOS data of a main board of an electronic device, wherein the electronic device comprises a control chip and a pin header, and the CMOS data clearing circuit comprises:

a controller, configured to generates a pulse signal and an operation signal; and

a connection port, having an input pin and an output pin, wherein the input pin is coupled to the controller, the output pin is coupled to a first pin of the pin header, the connection port conducts the input pin to the output pin in response to the operation signal, so as to transmit the pulse signal to the first pin of the pin header via the output pin, and the control chip clears the CMOS data according to the pulse signal received by the first pin.

2 . The CMOS data clearing circuit of claim 1 , wherein the pin header is disposed on an edge of the main board.

3 . The CMOS data clearing circuit of claim 1 , wherein when the pulse signal transitions from a high voltage value to a low voltage value, the control chip clears the CMOS data.

4 . The CMOS data clearing circuit of claim 3 , wherein a second pin of the pin header is coupled to a reference low voltage, and the low voltage value of the pulse signal is equal to a voltage value of the reference low voltage.

5 . The CMOS data clearing circuit of claim 1 , wherein the controller is further configured to generate a control signal, generate a delayed signal according to the control signal, and generate the pulse signal according to the control signal and the delayed signal.

6 . The CMOS data clearing circuit of claim 5 , wherein the controller comprises:

a first switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the input pin, and the second terminal of the first switch is coupled to a reference low voltage;

a first resistor, having a first terminal and a second terminal, wherein the first terminal of the first resistor receives the control signal, and the second terminal of the first resistor is coupled to the control terminal of the first switch;

a second resistor, coupled between the control terminal of the first switch and the reference low voltage;

a delay circuit, configured to receive the control signal and delay a timing of the control signal to generate the delayed signal; and

a second switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is coupled to the control terminal of the first switch, the second terminal of the second switch is coupled to the reference low voltage, and the control terminal of the second switch receives the delayed signal.

7 . The CMOS data clearing circuit of claim 6 , wherein the delay circuit comprises:

a delay resistor, having a first terminal and a second terminal, wherein the first terminal of the delay resistor receives the control signal, and the second terminal of the delay resistor is coupled to the control terminal of the second switch; and

a delay capacitor, coupled between the control terminal of the second switch and the reference low voltage.

8 . The CMOS data clearing circuit of claim 6 , wherein when a voltage value of the delayed signal is lower than or equal to a threshold voltage value of the second switch, the second switch is turned off, the first switch is turned on in response to a high voltage value of the control signal, so as to pull down a voltage value of the pulse signal to a low voltage value.

9 . The CMOS data clearing circuit of claim 8 , wherein when a voltage value of the delayed signal is higher than the threshold voltage value of the second switch, the second switch is turned on to turn off the first switch, causing the input pin to be floated.

10 . The CMOS data clearing circuit of claim 1 , further comprising:

an activation component, coupled to the controller, wherein when the activation component is operated, the controller provides the operation signal.