Granted Patent B2

US 12,650,766 · App. 18/409,661 · Granted Jun 9, 2026

Inventors: Johnny A. Lam (Firestone, CO); Samyukta Mudugal (Erie, CO); Sanjay Subbarao (Irvine, CA); Byron D. Harris (Mead, CO); Daniel A. Boals (Broomfield, CO)

Assignee: Micron Technology, Inc.

G06F3/0604G06F3/0655G06F3/0679

Abstract

Claims (55)

1 . A method comprising:

programming a data item to a first set of physical management units (MUs) associated with a memory sub-system in accordance with a first-pass programming operation of a multi-pass programming scheme;

updating an entry of a data structure to include a mapping that associates a first physical address associated with the first set of physical MUs with a set of virtual MUs associated with the memory sub-system;

detecting that a second-pass programming operation of the multi-pass programming scheme is initiated to program the data item to a second set of physical MUs associated with the memory sub-system; and

responsive to the detecting, updating the entry of the data structure to include an additional mapping that associates the set of virtual MUs with a second physical address associated with the second set of physical MUs.

2 . The method of claim 1 , further comprising:

adding an additional entry to an additional data structure associated with the memory sub-system, wherein the additional entry comprises an identifier associated with the set of virtual MUs.

3 . The method of claim 2 , wherein the data structure includes a virtual MU data structure that comprises mappings between addresses of physical MUs of the memory sub-system and virtual MUs of the memory sub-system, and wherein the additional data structure includes a logical-to-physical (L2P) table associated with the memory sub-system.

4 . The method of claim 1 , wherein updating the entry of the data structure to include the mapping that associates the first physical address with the set of virtual MUs comprises:

determining that the set of virtual MUs is available for allocation to the data item;

generating the mapping that associates the first physical address with the set of virtual MUs; and

updating a first field of the entry to include the generated mapping.

5 . The method of claim 4 , wherein updating the entry of the data structure to include the additional mapping that associates the set of virtual MUs with the second physical address comprises:

generating the additional mapping that associates the set of virtual MUs with the second physical address;

removing the mapping that associates the first physical address with the set of virtual MUs from the first field of the entry; and

updating the first field of the entry to include the generated additional mapping.

6 . The method of claim 1 , wherein the first set of physical MUs is associated with a first portion of the memory sub-system comprising memory cells having a first type, and wherein the second set of physical MUs is associated with a second portion of the memory sub-system comprising memory cells having a second type.

7 . The method of claim 6 , further comprising:

upon detecting that the programming of the data item to the first set of physical MUs in accordance with the first-pass programming operation is completed, updating the entry of the data structure to indicate that the data item is programmed to the memory cells having the first type; and

upon detecting that the programming of the data item to the second set of physical MUs in accordance with the second-pass programming operation is completed, updating the entry of the data structure to indicate that the data item is programmed to the memory cells having the second type.

8 . The method of claim 6 , wherein the memory cells having the first type comprise single level cells (SLCs) and the memory cells having the second type comprise at least one of a multi-level cell (MLC), a triple-level cell (TLC), or a quadruple-level cell (QLC).

9 . The method of claim 1 , further comprising:

responsive to the detecting that the second-pass programming operation is initiated, updating an additional entry of a memory conversion data structure to include a mapping associating the first physical address with the second physical address and the set of virtual MUs; and

responsive to detecting that the second-pass programming operation is completed, erasing the additional entry of the memory conversion data structure.

10 . The method of claim 1 , wherein the set of virtual MUs correspond to one or more block stripes of the memory sub-system.

11 . A system comprising:

one or more memory devices; and

a set of one or more processing devices coupled to each of the one or more memory devices, the set of one or more processing devices to perform operations comprising:

programming a data item to a first set of physical management units (MUs) associated with the one or more memory devices in accordance with a first-pass programming operation of a multi-pass programming scheme;

updating an entry of a data structure to include a mapping that associates a first physical address associated with the first set of physical MUs with a set of virtual MUs associated with the one or more memory devices;

detecting that a second-pass programming operation of the multi-pass programming scheme is initiated to program the data item to a second set of physical MUs associated with the one or more memory devices; and

responsive to the detecting, updating the entry of the data structure to include an additional mapping that associates the set of virtual MUs with a second physical address associated with the second set of physical MUs.

12 . The system of claim 11 , wherein the operations further comprise:

adding an additional entry to an additional data structure associated with the one or more memory devices, wherein the additional entry comprises an identifier associated with the set of virtual MUs.

13 . The system of claim 12 , wherein the data structure includes a virtual MU data structure that comprises mappings between addresses of physical MUs of the one or more memory devices and virtual MUs of the one or more memory devices, and wherein the additional data structure includes a logical-to-physical (L2P) table associated with the one or more memory devices.

14 . The system of claim 11 , wherein updating the entry of the data structure to include the mapping that associates the first physical address with the set of virtual MUs comprises:

determining that the set of virtual MUs is available for allocation to the data item;

generating the mapping that associates the first physical address with the set of virtual MUs; and

updating a first field of the entry to include the generated mapping.

15 . The system of claim 14 , wherein updating the entry of the data structure to include the additional mapping that associates the set of virtual MUs with the second physical address comprises:

generating the additional mapping that associates the set of virtual MUs with the second physical address;

removing the mapping that associates the first physical address with the set of virtual MUs from the first field of the entry; and

updating the first field of the entry to include the generated additional mapping.

16 . The system of claim 11 , wherein the first set of physical MUs is associated with a first portion of the one or more memory devices comprising memory cells having a first type, and wherein the second set of physical MUs is associated with a second portion of the one or more memory devices comprising memory cells having a second type.

17 . The system of claim 16 , wherein the operations further comprise:

upon detecting that the programming of the data item to the first set of physical MUs in accordance with the first-pass programming operation is completed, updating the entry of the data structure to indicate that the data item is programmed to the memory cells having the first type; and

upon detecting that the programming of the data item to the second set of physical MUs in accordance with the second-pass programming operation is completed, updating the entry of the data structure to indicate that the data item is programmed to the memory cells having the second type.

18 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a set of one or more processing devices, cause the set of one or more processing devices to perform operations comprising:

programming a data item to a first set of physical management units (MUs) associated with a memory sub-system in accordance with a first-pass programming operation of a multi-pass programming scheme;

updating an entry of a data structure to include a mapping that associates a first physical address associated with the first set of physical MUs with a set of virtual MUs associated with the memory sub-system;

detecting that a second-pass programming operation of the multi-pass programming scheme is initiated to program the data item to a second set of physical MUs associated with the memory sub-system; and

responsive to the detecting, updating the entry of the data structure to include an additional mapping that associates the set of virtual MUs with a second physical address associated with the second set of physical MUs.

19 . The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise:

adding an additional entry to an additional data structure associated with the memory sub-system, wherein the additional entry comprises an identifier associated with the set of virtual MUs.

20 . The non-transitory computer-readable storage medium of claim 19 , wherein the data structure includes a virtual MU data structure that comprises mappings between addresses of physical MUs of the memory sub-system and virtual MUs of the memory sub-system, and wherein the additional data structure includes a logical-to-physical (L2P) table associated with the memory sub-system.

Assignments (1)

Continuity (2)

References Cited (29)