Apparatuses including insulative structures of stack structures having different portions and related memory devices
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
1 . An apparatus, comprising:
a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the insulative structures individually comprising:
a first portion proximal to the conductive structures and comprising oxide material; and
a second portion distal to the conductive structures and comprising the oxide material, a thickness of the second portion relatively greater than a thickness of the first portion, and a density of the second portion differing from a density of the first portion;
discrete charge storage structures laterally adjacent to the conductive structures of the stack structure; and
dielectric material laterally adjacent to the conductive structures and the first portion of the insulative structures, the dielectric material directly physical contacting the conductive structures.
2 . The apparatus of claim 1 , wherein the dielectric material directly physically contacts the first portion and the second portion of the insulative structures.
3 . The apparatus of claim 1 , wherein the first portion and the second portion of the insulative structures are vertically adjacent one another, a material composition of the second portion differing from a material composition of the first portion.
4 . The apparatus of claim 1 , wherein the second portion of the insulative structures vertically intervenes between the discrete charge storage structures.
5 . The apparatus of claim 1 , wherein:
upper surfaces of the discrete charge storage structures are substantially coplanar with upper surfaces of the conductive structures of the stack structure; and
lower surfaces of the discrete charge storage structures are substantially coplanar with lower surfaces of the conductive structures of the stack structure.
6 . The apparatus of claim 1 , further comprising a channel material extending through the stack structure.
7 . An apparatus, comprising:
a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, the insulative structures comprising at least two different portions of dielectric material directly physically contacting one another along horizontal interfaces therebetween;
charge storage structures laterally adjacent to the conductive structures of the stack structure; and
charge block material between the charge storage structures and a respective conductive structure, the charge block material comprising:
a first portion extending within recessed regions in the insulative structures of the stack structure; and
a second portion extending outside the recessed regions in the insulative structures of the stack structure.
8 . The apparatus of claim 7 , further comprising:
tunnel dielectric material on inner side surfaces of the charge storage structures; and
liner material adjacent to the tunnel dielectric material, the liner material extending beyond upper and lower boundaries of segmented portions of the tunnel dielectric material.
9 . The apparatus of claim 7 , wherein the at least two different portions of the dielectric material comprises a first portion vertically intervening between a second portion and a third portion, inner side surfaces of the first portion extending beyond inner side surfaces of the second portion and the third portion.
10 . The apparatus of claim 7 , wherein the charge storage structures are vertically aligned with the insulative structures.
11 . The apparatus of claim 7 , wherein:
upper boundaries of segmented portions of the charge block material are substantially coincident with upper boundaries of individual conductive structures of the stack structure; and
lower boundaries of the segmented portions of the charge block material are substantially coincident with lower boundaries of the individual conductive structures.
12 . The apparatus of claim 7 , wherein at least portions of the charge block material extend beyond upper and lower boundaries of the conductive structures of the stack structure.
13 . The apparatus of claim 7 , wherein the at least two different portions of the dielectric material differ from one another in relative thickness.
14 . A memory device, comprising:
a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, at least some of the insulative structures comprising:
opposing portions directly contacting the conductive structures; and
a central portion separating the opposing portions from one another, a material composition of the central portion differing from a material composition of the opposing portions; and
charge storage structures laterally aligned with the conductive structures of the stack structure and comprising floating gates laterally adjacent to the conductive structures of the stack structure, portions of the floating gates extending beyond lateral side surfaces of the insulative structures of the stack structure.
15 . The memory device of claim 14 , further comprising an oxide-nitride-oxide structure laterally intervening between the charge storage structures and the conductive structures of the stack structure, discrete portions of an oxide material of the oxide-nitride-oxide structure vertically segmented by the insulative structures of the stack structure.
16 . The memory device of claim 14 , wherein a combined thickness of the opposing portions is relatively less than a thickness of the central portion of the insulative structures.
17 . The memory device of claim 14 , wherein the central portion directly vertically intervenes between the opposing portions of the insulative structures.
18 . The memory device of claim 14 , wherein the memory device comprises a NAND Flash memory device comprising memory cells.
19 . The memory device of claim 14 , further comprising a channel material extending through the stack structure.
20 . The memory device of claim 19 , further comprising a tunnel dielectric material positioned between the floating gates and the channel material.