Photolithography alignment process for bonded wafers
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
1. A method for forming an integrated chip, comprising:
performing an alignment process on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins;
bonding the first semiconductor workpiece to the second semiconductor workpiece;
determining a shift value between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece; and
forming a layer of an integrated circuit (IC) structure over the second semiconductor workpiece based at least in part on the shift value.
2. The method of claim 1 , wherein during the alignment process a first workpiece pin in the plurality of workpiece pins guides the second semiconductor workpiece over the first semiconductor workpiece.
3. The method of claim 1 , wherein before bonding the first semiconductor workpiece to the second semiconductor workpiece optical alignment is not performed between the first and second semiconductor workpieces.
4. The method of claim 3 , wherein the shift value is determined by transmitting light over the second semiconductor workpiece to the first semiconductor workpiece to determine locations of the first plurality of alignment marks and the second plurality of alignment marks.
5. The method of claim 1 , wherein forming the layer of the IC structure includes performing at least one photolithography process that is compensatively adjusted according to the shift value.
6. The method of claim 5 , wherein compensatively adjusting the at least one photolithography process comprises setting a location of one or more photomasks based at least in part on the shift value.
7. The method of claim 1 , further comprising:
performing a trimming process on the second semiconductor workpiece, thereby removing a notch in a substrate of the second semiconductor workpiece, wherein a notch is disposed at an outer edge of a substrate of the first semiconductor workpiece after the trimming process.
8. The method of claim 1 , wherein after bonding the first and second semiconductor workpieces each alignment mark in the second plurality of alignment marks directly overlies at least a portion of a corresponding alignment mark in the first plurality of alignment marks.
9. A method for forming an integrated chip, comprising:
performing a bonding process to bond a first semiconductor workpiece to a second semiconductor workpiece;
measuring a shift value between the first semiconductor workpiece and the second semiconductor workpiece;
depositing a layer of a semiconductor structure over the second semiconductor workpiece; and
performing a patterning process on the layer, wherein the patterning process includes setting a location of a photomask over the second semiconductor workpiece based at least in part on the shift value.
10. The method of claim 9 , further comprising:
forming a first plurality of marks on a first substrate of the first semiconductor workpiece;
forming a first interconnect structure on a second substrate of the second semiconductor workpiece; and
forming a second plurality of marks in a dielectric layer on the first interconnect structure;
wherein a bonding interface is disposed between the first substrate and the dielectric layer.
11. The method of claim 10 , further comprising:
wherein an outer region of the second semiconductor workpiece overhangs an outer edge of the first semiconductor workpiece; and
performing a trimming process to remove the outer region of the second semiconductor workpiece, wherein the patterning process is performed after the trimming process.
12. The method of claim 9 , further comprising:
forming a plurality of first semiconductor devices on a first surface of a substrate of the first semiconductor workpiece; and
forming a plurality of second semiconductor devices over and/or on a second surface of the substrate of the first semiconductor workpiece based at least in part on the shift value, wherein the first surface is opposite the second surface.
13. The method of claim 12 , wherein the plurality of first semiconductor devices are formed before measuring the shift value.
14. The method of claim 12 , further comprising:
forming a plurality of third semiconductor devices over the plurality of second semiconductor devices based at least in part on the shift value.
15. The method of claim 14 , wherein the plurality of first semiconductor devices and the plurality of second semiconductor devices are front-end of line (FEOL) devices, and wherein the plurality of third semiconductor devices are back-end of line (BEOL) devices.
16. A processing system, comprising:
a bonding device configured to bond a first semiconductor workpiece to a second semiconductor workpiece;
a shift measurement device configured to measure a shift value between the first semiconductor workpiece and the second semiconductor workpiece;
a photolithography device configured to perform one or more patterning processes to form one or more layers of a semiconductor structure over the second semiconductor workpiece; and
a controller configured to adjust parameters of the photolithography device during the one or more patterning processes based at least in part on the shift value.
17. The processing system of claim 16 , wherein the bonding device is configured to bond the first and second semiconductor workpieces without optical alignment, and wherein the shift measurement device is configured to measure the shift value based at least in part on a light sensor.
18. The processing system of claim 16 , wherein the shift value is stored in memory and provided to the controller and/or the photolithography device during the one or more patterning processes.
19. The processing system of claim 16 , wherein the bonding device comprises a plurality of pins configured to align the second semiconductor workpiece over the first semiconductor workpiece.
20. The processing system of claim 16 , wherein the one or more patterning processes are configured to form at least a portion of a plurality of semiconductor devices over the second semiconductor workpiece.