IP Library Granted Patent US 12,345,996
Granted Patent B2
US 12,345,996 · App. 18/421,034 · Granted Jul 1, 2025

Semiconductor substrate usable in an electrophoretic display device

Inventor: Hirotaka Hayashi (Tokyo, JP)
Assignee: Japan Display Inc.
G02F1/16766G02F1/133345G02F1/136227G02F1/167G02F1/16757H10D30/6755H10D86/423H10D86/441H10D86/60
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Quick Facts
Patent No.
US 12,345,996
App. No.
18/421,034
Granted
Jul 1, 2025
Kind
B2
Abstract

According to one embodiment, a semiconductor substrate, comprising, a first semiconductor layer and a second semiconductor layer that overlap a scanning line, an insulating layer that covers the first semiconductor layer and the second semiconductor layer, and a signal line, wherein the insulating layer has a first opening including a pair of long sides and a pair of short sides, the long sides of the first opening are parallel to the second direction, and the short sides of the first opening are parallel to the first direction, and the signal line is connected to the first semiconductor layer and the second semiconductor layer via the first opening.

Claims (45)

1. A substrate comprising:

a gate electrode:

a source electrode;

a drain electrode located next to the source electrode in a first direction;

a first oxide semiconductor;

a second oxide semiconductor located next to the first oxide semiconductor in a second direction intersecting the first direction;

a first insulating layer; and

a second insulating layer, wherein

both of the first oxide semiconductor and the second oxide semiconductor overlap the gate electrode,

the first insulating layer contacts both of the first oxide semiconductor and the second oxide semiconductor,

the source electrode contacts both of the first oxide semiconductor and the second oxide semiconductor via a first opening formed in the first insulating layer,

the drain electrode contacts both of the first oxide semiconductor and the second oxide semiconductor via a second opening formed in the first insulating layer,

the second insulating layer contacts the first insulating layer between the first opening and the second opening in the first direction,

both of the first opening and the second opening have a long axis extending in the second direction and a short axis extending in the first direction,

the first opening, which overlaps both of the first oxide semiconductor and the second oxide semiconductor, is a single opening, and

the second opening, which overlaps both of the first oxide semiconductor and the second oxide semiconductor, is a single opening.

2. The substrate of claim 1 , further comprising:

a third insulating layer, wherein

both of the first oxide semiconductor and the second oxide semiconductor are sandwiched between the first insulating layer and the third insulating layer,

the first insulating layer is provided between the second insulating layer and the third insulating layer, and

the second insulating layer contacts both of the source electrode and the drain electrode.

3. The substrate of claim 2 , wherein

the source electrode contacts the third insulating layer between the first oxide semiconductor and the second oxide semiconductor in the first opening, and

the drain electrode contacts the third insulating layer between the first oxide semiconductor and the second oxide semiconductor in the second opening.

4. The substrate of claim 3 , wherein

the gate electrode contacts the second insulating layer, and

the second insulating layer is provided between the gate electrode and the first insulating layer.

5. The substrate of claim 3 , wherein

the gate electrode contacts the third insulating layer, and

the third insulating layer is provided between the gate electrode and both of the first oxide semiconductor and the second oxide semiconductor.

6. The substrate of claim 3 , wherein

the gate electrode includes a first gate electrode and a second gate electrode,

the first gate electrode contacts the second insulating layer,

the second insulating layer is provided between the first gate electrode and the first insulating layer,

both of the first oxide semiconductor and the second oxide semiconductor overlap the first gate electrode,

the second gate electrode contacts the third insulating layer,

the third insulating layer is provided between the second gate electrode and both of the first oxide semiconductor and the second oxide semiconductor, and

both of the first oxide semiconductor and the second oxide semiconductor overlap the second gate electrode.

7. The substrate of claim 1 , wherein

both of the first oxide semiconductor and the second oxide semiconductor have a long axis extending in the first direction and a short axis extending in the second direction,

a part of the first opening is provided outside of both of the first oxide semiconductor and the second oxide semiconductor, and

a part of the second opening is provided outside of both of the first oxide semiconductor and the second oxide semiconductor.

8. The substrate of claim 1 , further comprising:

a pixel electrode, wherein

the drain electrode is connected to the pixel electrode.

Assignments (2)
CHANGE OF NAME Recorded Aug 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 073057/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2025
From: HAYASHI, HIROTAKA
To: JAPAN DISPLAY INC.
Reel/Frame 070631/0048 →
Priority Claims (1)
JP 2020-179100 · Oct 26, 2020 · national
Continuity (2)
Continuation 17451339 · Oct 19, 2021
Related Publication 20240160077A1 · May 16, 2024
References Cited (9)
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CN 103247644A · 2013 [cited by applicant]
JP H03009328A · 1991 [cited by applicant]
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JP 2020126218A · 2020 [cited by applicant]
Office Action issued on Mar. 12, 2024, in corresponding Chinese Application No. 202111207966.9, 14 pages. [cited by applicant]
Office Action issued on Apr. 2, 2024, in corresponding Japanese Application No. 2020-179100, 6 pages. [cited by applicant]