Tracking charge loss in memory sub-systems
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include computing an adjustment value of a threshold voltage offset associated with a block family of the memory device; determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to known valley margins of the memory device; and updating the threshold voltage offset.
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
computing an adjustment value of a threshold voltage offset associated with a block family of the memory device;
determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to valley margins of the memory device; and
updating the threshold voltage offset.
2. The system of claim 1 , wherein the operations further comprise:
responsive to determining that the adjustment value satisfies the threshold voltage criterion, scanning the block family.
3. The system of claim 1 , wherein a triggering event is a memory cell programming event associated with the block family.
4. The system of claim 1 , wherein the adjustment value is represented by a function of time raised to a power of a first coefficient and multiplied by a second coefficient, wherein at least one of the first and the second coefficients reflects a temperature of a memory component carrying one or more blocks of a plurality of blocks comprised by the block family.
5. The system of claim 1 , wherein the operations further comprise:
storing, on the memory device, metadata reflecting the adjustment value and the threshold voltage offset.
6. The system of claim 1 , wherein computing the adjustment value of the threshold voltage offset is performed by a hardware accelerator.
7. The system of claim 1 , wherein the block family is identified randomly from a plurality of blocks of the memory device.
8. A method comprising:
computing an adjustment value of a threshold voltage offset associated with a block family of a memory device;
determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to known valley margins of the memory device; and
updating the threshold voltage offset.
9. The method of claim 8 , further comprising:
responsive to determining that the adjustment value satisfies the threshold voltage criterion, scanning the block family.
10. The method of claim 8 , wherein a triggering event comprises a memory cell programming event associated with the block family.
11. The method of claim 8 , wherein the adjustment value is represented by a function of time raised to a power of a first coefficient and multiplied by a second coefficient, wherein at least one of the first and the second coefficients reflects a temperature of a memory component carrying one or more blocks of a plurality of blocks comprised by the block family.
12. The method of claim 8 , further comprising:
storing, on the memory device, metadata reflecting the adjustment value and the threshold voltage offset.
13. The method of claim 8 , wherein computing the adjustment value of the threshold voltage offset is performed by a hardware accelerator.
14. The method of claim 8 , wherein the block family is identified randomly from a plurality of blocks of the memory device.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
computing an adjustment value of a threshold voltage offset associated with a block
family of a memory device;
determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to known valley margins of the memory device; and
updating the threshold voltage offset.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:
responsive to determining that the adjustment value satisfies the threshold voltage criterion, scanning the block family.
17. The non-transitory computer-readable storage medium of claim 15 , wherein a triggering event comprises a memory cell programming event associated with the block family.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the adjustment value is represented by a function of time raised to a power of a first coefficient and multiplied by a second coefficient, wherein at least one of the first and the second coefficients reflects a temperature of a memory component carrying one or more blocks of a plurality of blocks comprised by the block family.
19. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:
storing, on the memory device, metadata reflecting the adjustment value and the threshold voltage offset.
20. The non-transitory computer-readable storage medium of claim 15 , wherein computing the adjustment value of the threshold voltage offset is performed by a hardware accelerator.