IP Library › Granted Patent US 12,547,561
Granted Patent B2
US 12,547,561 · App. 18/426,824 · Granted Feb 10, 2026

Using system memory to store initialization data for initialization of devices on a link

Inventors: Patricia G. Driever (Poughkeepsie, NY); Marco Kraemer (Sindelfingen, DE); Asha Kiran Bondalakunta (Bangalore, IN); Matthew J. Kalos (Tucson, AZ)
Assignee: International Business Machines Corporation
G06F13/1684G06F13/4221G06F2213/0026
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,547,561
App. No.
18/426,824
Granted
Feb 10, 2026
Kind
B2
Abstract

Provided are a computer program product, system, and method for using system memory to store initialization data for initialization of devices on a link. A link initialization memory area is initialized in a system memory of the first device. A bus address in a bus interface is provided that maps to the link initialization memory area. A first device writes first initialization data to the bus address to cause the first initialization data to be written to the link initialization memory area. A second device writes second initialization data over the bus interface to the bus address to cause the second initialization data to be written to the link initialization memory area. The first device and the second device communicate Input/Output (I/O) requests over the link in response to the writing of the first initialization data and the second initialization data to the link initialization memory area.

Claims (60)

1 . A computer program product for initializing a link between a first device and a second device, the computer program product comprising a computer readable storage medium having computer readable program code embodied in the first device and the second device that when executed performs operations, the operations comprising:

initializing a link initialization memory area in a system memory of the first device;

providing a bus address in a bus interface mapping to the link initialization memory area;

writing, by the first device, first initialization data to the bus address to cause the first initialization data to be written to the link initialization memory area;

writing, by the second device, second initialization data over the bus interface to the bus address to cause the second initialization data to be written to the link initialization memory area; and

communicating Input/Output (I/O) requests between the first device and the second device over the link in response to the writing of the first initialization data and the second initialization data to the link initialization memory area.

2 . The computer program product of claim 1 , wherein the computer readable program code in the first device is implemented in first link firmware in the first device, and wherein the computer readable program code in the second device is implemented in second link firmware in the second device.

3 . The computer program product of claim 2 , wherein the bus interface comprises a Peripheral Component Interconnect Express (PCIe) bus interface implemented in a PCIe card and the first link firmware and the second link firmware are implemented in processor complexes in the first device and the second device, respectively.

4 . The computer program product of claim 1 , wherein the operations further comprise:

enabling, by the first device, direct memory access (DMA) to the link initialization memory area; and

determining, by the second device, whether the DMA is enabled, wherein the second device writes to the link initialization memory area using the DMA in response to the determining that the DMA is enabled.

5 . The computer program product of claim 1 , wherein the initializing the link initialization memory area comprises:

configuring a first memory area for the first device in the link initialization memory area for the first device and a second memory area in the link initialization memory area for the second device, wherein the first device writes to the first memory area and reads from the second memory area during the link initialization, and wherein the second device writes to the second memory area and reads from the first memory area during the link initialization.

6 . The computer program product of claim 1 , wherein the operations further comprise:

determining, by the first device, whether the second device has written the second initialization data to the link initialization memory area; and

writing, by the first device, handshake complete for the first device in the link initialization memory area in response to determining that the second device has written the second initialization data to the link initialization memory area.

7 . The computer program product of claim 6 , wherein the operations further comprise:

writing, by the second device, data available for the second device in the link initialization memory area in response to writing the second initialization data to the link initialization memory area; and

determining, by the first device, whether the second device has written the data available to the link initialization memory area, wherein the first device determines whether the second device has written the second initialization data to the link initialization memory area in response to determining that the second device has written data available in the link initialization memory area.

8 . The computer program product of claim 6 , wherein the operations further comprise:

writing, by the first device, heartbeat values for the first device in the link initialization memory area in response to determining that the second device has written the second initialization data to the link initialization memory area; and

writing, by the second device, heartbeat values for the second device in the link initialization memory area in response to determining that the first device has written the first initialization data to the link initialization memory area.

9 . The computer program product of claim 1 , wherein the first device comprises a host system and the second device comprises a storage controller managing a storage used by the first device to store data.

10 . The computer program product of claim 1 , wherein the I/O requests comprise synchronous I/O operations between the first device and the second device over the link.

11 . A system for initializing a link between a first device and a second device, comprising:

a processor;

a system memory accessed by the processor; and

a computer readable storage medium having computer readable program code embodied in the first device that when executed performs operations, the operations comprising:

initializing a link initialization memory area in the system memory of the first device;

providing a bus address in a bus interface mapping to the link initialization memory area;

writing, by the first device, first initialization data to the bus address to cause the first initialization data to be written to the link initialization memory area;

receiving second initialization data from the second device over the bus interface to write to the bus address to cause the second initialization data to be written to the link initialization memory area; and

communicating Input/Output (I/O) requests between the first device and the second device over the link in response to the writing of the first initialization data and the second initialization data to the link initialization memory area.

12 . The system of claim 11 , wherein the operations further comprise:

enabling, by the first device, direct memory access (DMA) to the link initialization memory area, wherein the second device determines whether the DMA is enabled, and wherein the second device writes to the link initialization memory area using the DMA in response to the determining that the DMA is enabled.

13 . The system of claim 11 , wherein the initializing the link initialization memory area comprises:

configuring a first memory area for the first device in the link initialization memory area for the first device and a second memory area in the link initialization memory area for the second device, wherein the first device writes to the first memory area and reads from the second memory area during the link initialization, and wherein the second device writes to the second memory area and reads from the first memory area during the link initialization.

14 . The system of claim 11 , wherein the operations further comprise:

determining, by the first device, whether the second device has written the second initialization data to the link initialization memory area; and

writing, by the first device, handshake complete for the first device in the link initialization memory area in response to determining that the second device has written the second initialization data to the link initialization memory area.

15 . The system of claim 14 , wherein the operations further comprise:

writing, by the second device, data available for the second device in the link initialization memory area in response to writing the second initialization data to the link initialization memory area; and

determining, by the first device, whether the second device has written the data available to the link initialization memory area, wherein the first device determines whether the second device has written the second initialization data to the link initialization memory area in response to determining that the second device has written data available in the link initialization memory area.

16 . A method for initializing a link between a first device and a second device, comprising:

initializing a link initialization memory area in a system memory of the first device;

providing a bus address in a bus interface mapping to the link initialization memory area;

writing, by the first device, first initialization data to the bus address to cause the first initialization data to be written to the link initialization memory area;

writing, by the second device, second initialization data over the bus interface to the bus address to cause the second initialization data to be written to the link initialization memory area; and

communicating Input/Output (I/O) requests between the first device and the second device over the link in response to the writing of the first initialization data and the second initialization data to the link initialization memory area.

17 . The method of claim 16 , further comprising:

enabling, by the first device, direct memory access (DMA) to the link initialization memory area; and

determining, by the second device, whether DMA is enabled, wherein the second device writes to the link initialization memory area using DMA in response to the determining that the DMA is enabled.

18 . The method of claim 16 , wherein the initializing the link initialization memory area comprises:

configuring a first memory area for the first device in the link initialization memory area for the first device and a second memory area in the link initialization memory area for the second device, wherein the first device writes to the first memory area and reads from the second memory area during the link initialization, and wherein the second device writes to the second memory area and reads from the first memory area during the link initialization.

19 . The method of claim 16 , further comprising:

determining, by the first device, whether the second device has written the second initialization data to the link initialization memory area; and

writing, by the first device, handshake complete for the first device in the link initialization memory area in response to determining that the second device has written the second initialization data to the link initialization memory area.

20 . The method of claim 19 , further comprising:

writing, by the second device, data available for the second device in the link initialization memory area in response to writing the second initialization data to the link initialization memory area; and

determining, by the first device, whether the second device has written the data available to the link initialization memory area, wherein the first device determines whether the second device has written the second initialization data to the link initialization memory area in response to determining that the second device has written data available in the link initialization memory area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2024
From: DRIEVER, PATRICIA G.; KRAEMER, MARCO; BONDALAKUNTA, ASHA KIRAN; KALOS, MATTHEW J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 066300/0547 →
Continuity (1)
Related Publication 20250245177A1 · Jul 31, 2025
References Cited (21)
US 5003465A · Chisholm et al. · 1991 [cited by applicant]
US 10009423B2 · Craddock et al. · 2018 [cited by applicant]
US 10009424B2 · Craddock et al. · 2018 [cited by applicant]
US 10068000B2 · Craddock et al. · 2018 [cited by applicant]
US 10068001B2 · Craddock et al. · 2018 [cited by applicant]
US 10133691B2 · Brewer et al. · 2018 [cited by applicant]
US 10229084B2 · Brewer · 2019 [cited by examiner]
US 10282192B1 · Ayoub · 2019 [cited by examiner]
US 10922068B1 · Radjabi · 2021 [cited by examiner]
US 11311801B2 · Colenbrander · 2022 [cited by examiner]
US 20170249167A1 · Izumi · 2017 [cited by examiner]
US 20200278935A1 · Borikar et al. · 2020 [cited by applicant]
“End-to-End Data Access Policies and Guarantees Span Across Stack Components,” IP.com, IP.com No. IPCOM000270703D, Aug. 1, 2022, 8 pp. [cited by applicant]
“IOQ-Based Differential Security Model for NVMe Storage System,” IP.com, IP.com No. IPCOM000265704D, May 7, 2021, 6 pp. [cited by applicant]
“Method for Improved Inter-Tier Migration Management with NVMe Drives,” IP.com, IP.com No. IPCOM000266527D, Jul. 26, 2021, 9 pp. [cited by applicant]
“Parallel Synchronous Transmission Using GPIO and DMA,” St Microelectronics, AN4666 Application Note, Jan. 2016, 30 pp. [cited by applicant]
“Staged NVMe in a Primary/Secondary Relationship,” IP.com, IP.com No. IPCOM000268073D, Dec. 21, 2021, 4 pp. [cited by applicant]
D. Riedy, et al., “Getting Started with IBM zHyperLink for z/OS,” IBM Corporation, IBM Red Paper, Document REDP-5493-01, Apr. 2022, 152 pp. [cited by applicant]
J. Zhu, et al., “uDMA: An Efficient User-Level DMS for NVMe SSDs,” Applied Sciences, 2023, 14 pp. [cited by applicant]
M.A. Ahmed, et al., “Design and Implementation of a Direct Memory Access Controller for Embedded Applications,” IJTech, International Journal of Technology 10(2): 309-319, 2019, 11 pp. [cited by applicant]
S.K. Singh, “Computer Organization and Architecture,” Indian Institute of Information Technology, 2020, 21 pp. [cited by applicant]