IP Library › Granted Patent US 12,475,035
Granted Patent B2
US 12,475,035 · App. 18/429,064 · Granted Nov 18, 2025

Methods and apparatus to facilitate immutable configuration of memory devices

Inventors: Prasanth Viswanathan Pillai (Bangalore, IN); Rajasekhar Reddy Allu (Plano, TX); David P. Foley (Sugar Land, TX); Amritpal S. Mundra (Allen, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
G06F12/0246
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Quick Facts
Patent No.
US 12,475,035
App. No.
18/429,064
Granted
Nov 18, 2025
Kind
B2
Abstract

Methods, apparatus, systems, and articles of manufacture are described corresponding to immutable configuration of memory devices. An example memory includes a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and a controller coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.

Claims (32)

1 . A device comprising:

a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable;

a processor coupled to the memory bank; and

a controller coupled to the memory bank, the controller configured to, based on receiving a write operation directed to a location of the memory bank, output an alert to the processor, the alert including the location, and, based on receiving an indication that the location is immutable, prevent the write operation directed to the location of the memory bank.

2 . The device of claim 1 , wherein the memory bank is flash memory.

3 . The device of claim 1 , wherein the second portion is within a keystore region of the memory bank.

4 . The device of claim 1 , wherein the first portion is within a data region of the memory bank.

5 . The device of claim 1 , wherein the controller is configured to output the configuration information to the processor, and the processor is configured to determine that the location is immutable based on the configuration information.

6 . The device of claim 1 , wherein the second portion includes a plurality of memory cells, wherein each of the memory cells corresponds to a respective location of the memory bank.

7 . The device of claim 6 , wherein each of the memory cells is configured to store a respective value indicating whether the respective location of the memory bank is immutable.

8 . An apparatus comprising:

memory including a first portion of memory and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and

processing circuitry configured to:

obtain the configuration information from the memory;

store the configuration information in a register; and

based on an operation directed to the first portion of the memory, receive an alert indicating the operation and a location in the first memory to which the operation is directed, compare the location in the alert to the configuration information in the register, and send a response that specifies whether to prevent the operation to the first portion of the memory based on the configuration information.

9 . The apparatus of claim 8 , wherein the memory is non-volatile, rewritable memory.

10 . The apparatus of claim 8 , wherein the second portion is within a keystore region of the memory.

11 . The apparatus of claim 8 , wherein the first portion is within a data region of the memory.

12 . The apparatus of claim 8 , wherein the memory is configured to send the alert.

13 . The apparatus of claim 8 , wherein the identification is a first identification, the response is a first response, and the operation is a first operation, the processing circuitry configured to, based on a second identification of a second operation to a third portion of the memory different than the first portion, send a second response to allow the operation to the third portion of the memory.

14 . The apparatus of claim 8 , wherein the processing circuitry is to, based on an alert that the first portion of the memory has expanded, update the configuration information in the register.

15 . An apparatus comprising:

memory including a first portion of memory and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and

a memory controller to at least one of instantiate or execute computer readable instructions to:

based on an instruction corresponding to a write operation to write data to a location of the memory, output an alert including the location of the memory; and

based on a response to the alert, determine whether to prevent the write operation to the location of the memory.

16 . The apparatus of claim 15 , wherein the response to the alert specifies to prevent the write operation.

17 . The apparatus of claim 15 , wherein the memory controller is configured to, based on an indication to expand the first portion of the memory, write expanded configuration information into the second portion of the memory.

18 . The apparatus of claim 15 , wherein the memory is non-volatile, rewritable memory.

19 . The apparatus of claim 15 , wherein the second portion is within a keystore region of the memory.

20 . The apparatus of claim 15 , wherein the first portion is within a data region of the memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2024
From: VISWANATHAN PILLAI, PRASANTH; ALLU, RAJASEKHAR REDDY; FOLEY, DAVID P.; MUNDRA, AMRITPAL S.
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 066480/0528 →
Continuity (2)
Provisional Application 63532099 · Aug 11, 2023
Related Publication 20250053507A1 · Feb 13, 2025
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