Memory compaction management in memory devices
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value;
responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and
causing the memory device to copy the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
2. The system of claim 1 , wherein the operations further comprise:
responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
3. The system of claim 1 , wherein the operations further comprise:
determining whether the data integrity metric value satisfies a threshold criterion.
4. The system of claim 1 , wherein the source set of memory cells are configured as single-level cell (SLC) memory.
5. The system of claim 1 , wherein the destination set of memory cells are configured as higher-level cell (HLC) memory.
6. The system of claim 1 , wherein the data integrity metric value reflects at least one of a bit error count (BEC) value or a raw bit error rate (RBER) value.
7. The system of claim 1 , wherein the operations further comprise:
performing the data integrity check on the source set of memory cells responsive to determining that a flag is set.
8. A method, comprising:
performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value;
responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and
causing a memory device to copy the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
9. The method of claim 8 , further comprising:
responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
10. The method of claim 8 , further comprising:
determining whether the data integrity metric value satisfies a threshold criterion.
11. The method of claim 8 , wherein the source set of memory cells are configured as single-level cell (SLC) memory.
12. The method of claim 11 , wherein the destination set of memory cells are configured as higher-level cell (HLC) memory.
13. The method of claim 8 , wherein the data integrity metric value reflects at least one of a bit error count (BEC) value or a raw bit error rate (RBER) value.
14. The method of claim 8 , further comprising:
performing the data integrity check on the source set of memory cells responsive to determining that a flag is set.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, performs operations comprising:
performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value;
responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and
causing a memory device to copy the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:
responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
17. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:
determining whether the data integrity metric value satisfies a threshold criterion.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the source set of memory cells are configured as single-level cell (SLC) memory and the destination set of memory cells are configured as higher-level cell (HLC) memory.
19. The non-transitory computer-readable storage medium of claim 15 , wherein the data integrity metric value reflects at least one of a bit error count (BEC) value or a raw bit error rate (RBER) value.
20. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:
performing the data integrity check on the source set of memory cells responsive to determining that a flag is set.