IP Library Granted Patent US 12,400,688
Granted Patent B2
US 12,400,688 · App. 18/438,709 · Granted Aug 26, 2025

Assemblies comprising memory cells and select gates; and methods of forming assemblies

Inventor: Ugo Russo (Boise, ID)
Assignee: Micron Technology, Inc.
G11C7/1006G11C7/1096G11C8/12G11C16/08G11C19/32H10B41/35H10B43/27G11C11/5621
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Quick Facts
Patent No.
US 12,400,688
App. No.
18/438,709
Granted
Aug 26, 2025
Kind
B2
Abstract

Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

Claims (87)

1. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level, the select gate configuration comprising a conductive liner surrounding a conductive core; and

a conductive interconnect extending through an uppermost surface of the channel material pillar.

2. The assembly of claim 1 wherein the conductive interconnect extends only partially into the channel material pillar.

3. The assembly of claim 1 wherein the conductive interconnect couples the channel material pillar to other circuitry.

4. The assembly of claim 1 further comprising vertically-extending conductive structures which electrically couple the conductive levels.

5. The assembly of claim 4 wherein the vertically-extending conductive structures extend through the insulative level over the stack.

6. The assembly of claim 1 further comprising an insulative layer extending over the alternating dielectric levels and conductive levels.

7. The assembly of claim 6 wherein the conductive interconnect extends into insulative layer.

8. The assembly of claim 1 further comprising an insulative layer extending over channel material pillars.

9. The assembly of claim 1 wherein the select gate configuration comprises a first conductive gate structure and a second conductive gate structure that comprises a different structural configuration relative to the first conductive gate structure.

10. The assembly of claim 1 further comprising an insulative liner against the insulative level.

11. The assembly of claim 1 further comprising an insulative liner over the insulative level and against an uppermost surface of the channel material pillar.

12. The assembly of claim 1 further comprising an insulative liner over the select gate configuration and the conductive interconnect extends through the insulative liner.

13. The assembly of claim 12 further comprising insulative material over the insulative liner and the conductive interconnect extends into the insulative material.

14. The assembly of claim 1 further comprising protective capping material over the select gate configuration and the conductive interconnect extends into the protective capping material.

15. The assembly of claim 1 further comprising dielectric material over the select gate configuration and the conductive interconnect extends into the dielectric material.

16. The assembly of claim 1 further comprising a level of conductive material in between the at least two of the conductive levels.

17. The assembly of claim 16 wherein the level of the conductive material is differently configured than either of the at least two of the conductive levels.

18. The assembly of claim 1 further comprising a gate level between the at least two of the conductive levels.

19. The assembly of claim 1 further comprising insulative material and conductive material between the at least two of the conductive levels.

20. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar;

wherein the select gate configuration comprises a first conductive gate structure and a second conductive gate structure laterally spaced from one another by an intervening insulative region;

wherein the first and second conductive gate structures have vertically-spaced conductive regions separated from one another by dielectric regions; and

vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

21. The assembly of claim 20 wherein the vertically-extending conductive structures extend through the intervening insulative region.

22. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar;

wherein the select gate configuration comprises a first conductive gate structure and a second conductive gate structure laterally spaced from one another by an intervening insulative region;

an insulative layer extending through the intervening insulative region and extending over the alternating dielectric levels and conductive levels; and

wherein the conductive interconnect extends into insulative layer.

23. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar; and

an insulative liner against the insulative level.

24. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar; and

an insulative liner over the insulative level and against an uppermost surface of the channel material pillar.

25. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar; and

an insulative liner over the select gate configuration and the conductive interconnect extends through the insulative liner.

26. The assembly of claim 25 further comprising insulative material over the insulative liner and the conductive interconnect extends into the insulative material.

27. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar; and

protective capping material over the select gate configuration and the conductive interconnect extends into the protective capping material.

28. An assembly, comprising:

a stack comprising alternating dielectric levels and conductive levels;

a channel material pillar extending through the stack;

memory cells along the channel material pillar;

an insulative level over the stack;

a select gate configuration over the insulative level;

a conductive interconnect extending through an uppermost surface of the channel material pillar; and

dielectric material over the select gate configuration and the conductive interconnect extends into the dielectric material.

Continuity (5)
Continuation 17499218 · Oct 12, 2021
Division 16810058 · Mar 5, 2020
Division 15926427 · Mar 20, 2018
Provisional Application 62609884 · Dec 22, 2017
Related Publication 20240185897A1 · Jun 6, 2024
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