Using built-in self test or test results to identify weak memory bits and enable assist circuits when necessary
View Patent ↗A semiconductor device and a method of operating the semiconductor device and circuit are disclosed. In one aspect, the semiconductor device includes a memory array comprising a first memory cell and a second memory cell. The second memory cell has an operational characteristic different than that of the first memory cell. The semiconductor device includes a first write circuit configured to write first data to the first memory cell. The semiconductor device includes a second write circuit configured to write second data to the second memory cell, wherein the second write circuit is selectively configured to compensate for the operational characteristic of the second memory cell.
1 . A semiconductor device, comprising:
a memory array comprising a first memory cell and a second memory cell, the second memory cell having an operational characteristic different than that of the first memory cell;
a first write driver circuit configured to write first data to the first memory cell, the first write driver circuit coupled with a first write assist enable circuit;
a second write driver circuit configured to write second data to the second memory cell, wherein the second write driver circuit is coupled to a second write assist enable circuit; and
a write assist configuration circuit configured to shift configuration data through a shift register of the first write assist enable circuit and the second write assist enable circuit to designate the second write driver circuit for activation, causing the second write assist enable circuit to configure the second write driver circuit to compensate for the operational characteristic of the second memory cell.
2 . The semiconductor device of claim 1 , wherein the first memory cell and the second memory cell each comprise a respective bit cell in the memory array.
3 . The semiconductor device of claim 1 , wherein the first write driver circuit is configured to operate at a first voltage to write the first data to the first memory cell and the second write driver circuit is configured to operate at a second voltage to write the second data to the second memory cell.
4 . The semiconductor device of claim 3 , further comprising a register storing control data that indicates the first write driver circuit is to operate at the first voltage and the second write driver circuit is to operate at the second voltage.
5 . The semiconductor device of claim 1 , wherein the first write assist enable circuit comprises a latch configured to receive a value from a shift register of the first write assist enable circuit and cause the second write driver circuit to operate using a second voltage.
6 . The semiconductor device of claim 5 , wherein the latch causes the second write driver circuit to operate using the second voltage based on a column address of the second memory cell.
7 . The semiconductor device of claim 1 , further comprising:
an address match circuit configured to produce a write assist enable signal upon receiving a write address corresponding to the second memory cell, wherein the second write driver circuit is configured to compensate for the operational characteristic of the second memory cell based on the write assist enable signal.
8 . The semiconductor device of claim 1 , further comprising a multiplexer circuit configured to receive a write signal from the second write driver circuit and provide the write signal to one of a first column or a second column, the first column comprising the second memory cell.
9 . The semiconductor device of claim 1 , wherein the first write driver circuit is coupled to a first column comprising the first memory cell and the second write driver circuit is coupled to a second column comprising the second memory cell.
10 . A memory circuit, comprising:
a write driver device configured to write input data to one of a first column or a second column of a memory array;
a write assist circuit configured to cause the write driver device to selectively operate at one of a first voltage or a second voltage;
a write assist enable circuit comprising a shift register and configured to activate the write assist circuit based on an indication that the first column or the second column comprises a memory cell having a defect; and
a write assist configuration circuit configured to shift configuration data through the shift register of the write assist enable circuit, causing the write assist enable circuit to designate the first column or the second column as having the defect.
11 . The memory circuit of claim 10 , further comprising:
a multiplexer device configured to receive a write signal from the write driver device and provide the write signal to one of the first column or the second column of the memory array, the first column or the second column selected based on a column address signal.
12 . The memory circuit of claim 11 , wherein the write assist enable circuit is configured to activate the write assist circuit further based on the column address signal matching a column address of the memory cell having the defect.
13 . The memory circuit of claim 10 , wherein the memory cell having the defect is defined within a first row of the memory array, the memory circuit further comprising:
a row address match circuit configured to generate a row enable signal upon detecting a match between an input row address and an address of the first row, write assist enable circuit configured to activate the write assist circuit further based on the row enable signal.
14 . The memory circuit of claim 13 , further comprising:
a multiplexer device configured to receive a write signal from the write driver device and provide the write signal to one of the first column or the second column of the memory array, the first column or the second column selected based on a column address signal.
15 . The memory circuit of claim 14 , wherein the write assist enable circuit is configured to activate the write assist circuit further based on the column address signal matching a column address of the memory cell having the defect.
16 . The memory circuit of claim 10 , wherein the write assist circuit is further configured to cause the write driver device to produce a boosted write voltage for writing to the memory cell having the defect.
17 . The memory circuit of claim 10 , wherein the write assist circuit is further configured to cause the write driver device to reduce a ground voltage for writing to the memory cell having the defect.
18 . A method, comprising:
shifting, by a write assist configuration circuit, configuration data through a shift register of a first write assist enable circuit and a second write assist enable circuit, the configuration data comprising an indication that a memory cell of a memory array has a predetermined operational characteristic;
detecting, by the first write assist enable circuit, a write operation for a row or column of the memory array including the memory cell having the predetermined operational characteristic; and
selectively activating, by the first write assist enable circuit, a write assist circuit to compensate for the predetermined operational characteristic of the memory cell during the write operation based on the indication.
19 . The method of claim 18 , wherein detecting the write operation comprises comparing an input column address for the write operation to a column address of the memory cell having the predetermined operational characteristic.
20 . The method of claim 18 , wherein detecting the write operation comprises comparing an input row address for the write operation to a row address of the memory cell having the predetermined operational characteristic.