Integrated circuit memory with write assist
An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4 . The power supply control circuit includes a first gate 26 and a second gate 28 . The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2 . The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2 . Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made. If individual memory cells 2 tend to resist changes in their state more strongly, then they will tend to draw more current which will in turn result in a larger virtual supply voltage dip which will assist more strongly in encouraging those memory cells 2 to change state.
1. An integrated circuit memory comprising:
at least one memory cell having a first state and a second state corresponding to storage of different values of a data bit; and
a power supply control circuit operable to supply power to said at least one memory cell and having a supply input coupled to a power source and a supply output coupled to said at least one memory cell; wherein
said power supply control circuit includes at least a first gate and a second gate and is responsive to a write assist signal to switch at least one of said first gate and said second gate such that:
when not writing to said at least one memory cell said power supply control circuit provides a low resistance path between said supply input and said supply output; and
when writing to said at least one memory cell said power supply control circuit provides a high resistance path, with a resistance greater than said low resistance path, between said supply input and said supply output so that said at least one memory cell is more readily switched between said first state and said second state.
2. An integrated circuit memory as claimed in claim 1 , wherein said first gate is switched to a conductive state by said write assist signal when not writing to said at least one memory cell.
3. An integrated circuit memory as claimed in claim 1 , wherein said first gate is switched to a non-conductive state by said write assist signal when writing to said at least one memory cell.
4. An integrated circuit memory as claimed in claim 1 , wherein said second gate remains in a conductive state both when writing to said at least one memory cell and when not writing to said at least one memory cell.
5. An integrated circuit memory as claimed in claim 1 , wherein said first gate has a lower resistance when conductive than said second gate when conductive.
6. An integrated circuit memory as claimed in claim 1 , wherein, if said at least one memory cell has an increased opposition to changing between said first state and said second state and thereby draws more current through said power supply control circuit whilst changing, then said high resistance path through said power supply control circuit serves to further reduce a supply voltage level at said supply output thereby assisting in changing said at least one memory cell between said first state and said second state.
7. An integrated circuit memory as claimed in claim 1 , wherein said power supply control circuit supplies power to a plurality of memory cells.
8. An integrated circuit memory as claimed in claim 7 , wherein said integrated circuit memory comprises a plurality of columns each formed of a plurality of memory cells and said power supply control circuit is shared by a plurality of memory cells within a column.
9. An integrated circuit memory as claimed in claim 1 , wherein said at least one memory cell comprises a pair of cross-coupled invertors.
10. An integrated circuit memory as claimed in claim 9 , wherein a pair of bit lines apply a bit value to change a data value stored by said at least one memory cell by forcing said cross-coupled invertors to switch between said first state and said second state.
11. An integrated circuit memory as claimed in claim 1 , wherein said at least one memory cell is a SRAM memory cell.
12. An integrated circuit memory as claimed in claim 1 , wherein said integrated circuit memory is a single ported integrated circuit memory.
13. An integrated circuit memory as claimed in claim 1 , wherein said write assist signal is generated by decoding at least a portion of an address value supplied to said integrated circuit memory specifying one or more data values to be written.
14. A method of writing data in an integrated circuit memory, said method comprising the steps of:
connecting a memory cell to a supply input via a power supply control circuit having at least a first gate and a second gate, at least one of said first gate and said second gate being switched between a conductive state and a non-conductive state by a write assist signal;
when not writing to a memory cell, switching said power supply control circuit to provide a low resistance path between said memory cell and said supply input; and when writing to said memory cell, switching said power supply control circuit to provide a high resistance path, with a resistance greater than said low resistance path, between said memory cell and said supply input.
15. A method as claimed in claim 14 , wherein said first gate is switched to a conductive state by said write assist signal when not writing to said memory cell.
16. A method as claimed in claim 14 , wherein said first gate is switched to a non-conductive state by said write assist signal when writing to said memory cell.
17. A method as claimed in claim 14 , wherein said second gate remains in a conductive state both when writing to said memory cell and when not writing to said memory cell.
18. A method as claimed in claim 14 , wherein said first gate has a lower resistance when conductive than said second gate when conductive.
19. A method as claimed in claim 14 , wherein, if said memory cell has an increased opposition to changing between said first state and said second state and thereby draws more current through said power supply control circuit whilst changing, then said high resistance path through said power supply control circuit serves to further reduce a supply voltage level at said memory cell thereby assisting in changing said memory cell between said first state and said second state.
20. A method as claimed in claim 14 , wherein said power supply control circuit supplies power to a plurality of memory cells.
21. A method as claimed in claim 20 , wherein said integrated circuit memory comprises a plurality of columns each formed of a plurality of memory cells and said power supply control circuit is shared by a plurality of memory cells within a column.
22. A method as claimed in claim 14 , wherein said memory cell comprises a pair of cross-coupled invertors.
23. A method as claimed in claim 22 , wherein a pair of bit lines apply a bit value to change a data value stored by said memory cell by forcing said cross-coupled invertors to switch between said first state and said second state.
24. A method as claimed in claim 14 , wherein said memory cell is a SRAM memory cell.
25. A method as claimed in claim 14 , wherein said integrated circuit memory is a single ported integrated circuit memory.
26. A method as claimed in claim 14 , wherein said write assist signal is generated by decoding at least a portion of an address value supplied to said integrated circuit memory specifying one or more data values to be written.