Integrated circuit device with low threshold voltage
A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.
1. A device, comprising:
a first structure that includes:
a first portion of a substrate;
a first stack of nano-structures disposed over the first portion of the substrate;
a first nitrogen-containing layer disposed between the nano-structures in the first stack; and
a first work function metal layer disposed between the nano-structures in the first stack, wherein the first work function metal layer is separated from the first nitrogen-containing layer by one or more other layers, and wherein the one or more other layers include at least an n-type work function metal layer; and
a second structure that includes:
a second portion of the substrate;
a second stack of nano-structures disposed over the second portion of the substrate;
a second nitrogen-containing layer disposed between the nano-structures in the second stack, wherein the first nitrogen-containing layer and the second nitrogen-containing layer have substantially similar material compositions; and
a second work function metal layer disposed between the nano-structures in the second stack, wherein the second work function metal layer and the first work function metal layer have substantially similar material compositions, and wherein the second work function metal layer is in physical contact with the second nitrogen-containing layer.
2. The device of claim 1 , wherein:
the first stack of nano-structures include channels of an n-type gate-all-around (GAA) transistor; and
the second stack of nano-structures include channels of a p-type (GAA) transistor.
3. The device of claim 1 , wherein the first nitrogen-containing layer and the second nitrogen-containing layer each contain titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN).
4. The device of claim 1 , wherein:
the first structure further includes a first fill metal and a first capping layer disposed between the first fill metal and the first work function metal layer;
the second structure further includes a second fill metal and a second capping layer disposed between the second fill metal and the second work function metal layer;
the first fill metal and the second fill metal have substantially similar material compositions; and
the first capping layer and the second capping layer have substantially similar material compositions.
5. The device of claim 1 , wherein the first work function metal layer and the second work function metal layer each include a p-type work function metal.
6. The device of claim 5 , wherein the p-type work function metal contains an unoxidized metal and a metal oxide.
7. The device of claim 6 , wherein:
the unoxidized metal includes ruthenium; and
the metal oxide include ruthenium oxide.
8. The device of claim 6 , wherein:
the unoxidized metal includes iridium; and
the metal oxide include iridium oxide.
9. The device of claim 5 , wherein the p-type work function metal contains a metal oxide but no unoxidized metal.
10. The device of claim 9 , wherein the metal oxide includes ruthenium oxide or iridium oxide.
11. A device, comprising:
an n-type gate-all-around (GAA) transistor that includes:
a first active region;
a first stack of semiconductor nano-layers disposed over the first active region;
a first nitrogen-containing layer disposed between the semiconductor nano-layers in the first stack;
a first work function metal layer disposed between the semiconductor nano-layers in the first stack, wherein the first work function metal layer contains a p-type work function metal; and
one or more additional layers disposed between the first nitrogen-containing layer and the first work function metal layer; and
a p-type GAA transistor that includes:
a second active region;
a second stack of semiconductor nano-layers disposed over the second active region;
a second nitrogen-containing layer disposed between the semiconductor nano-layers in the second stack, wherein the first nitrogen-containing layer and the second nitrogen-containing layer include a same type of nitrogen-containing material; and
a second work function metal layer disposed between the semiconductor nano-layers in the second stack and in direct contact with the second nitrogen-containing layer, wherein the second work function metal layer also contains the p-type work function metal.
12. The device of claim 11 , wherein at least some of the one or more additional layers do not contain the p-type work function metal.
13. The device of claim 11 , wherein the first nitrogen-containing layer and the second nitrogen-containing layer each contain titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN).
14. The device of claim 11 , wherein the one or more additional layers contain Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN.
15. The device of claim 11 , wherein the p-type work function metal contains an unoxidized metal and a metal oxide.
16. The device of claim 15 , wherein:
the unoxidized metal includes ruthenium or iridium; and
the metal oxide include ruthenium oxide or iridium oxide.
17. The device of claim 11 , wherein the p-type work function metal consists of ruthenium oxide or iridium oxide.
18. A device, comprising:
an n-type gate-all-around (GAA) transistor that includes:
a first layer that contains titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN);
a first p-type work function metal layer; and
an n-type work function metal layer disposed between the first layer and the first p-type work function metal layer, wherein the n-type work function metal layer contains Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN; and
a p-type GAA transistor that includes:
a second layer having a same material composition as the first layer; and
a second p-type work function metal layer that is in direct physical contact with the second layer, wherein the second p-type work function metal layer has a same material composition as the first p-type work function metal layer.
19. The device of claim 18 , wherein the first p-type work function metal layer and the second p-type work function metal layer each include ruthenium oxide or iridium oxide.
20. The device of claim 19 , wherein the first p-type work function metal layer and the second p-type work function metal layer are each free of unoxidized metals.